公开(公告)号：US20230397338A1

公开(公告)日：2023-12-07

申请号：US18449095

申请日：2023-08-14

Applicant: TDK Corporation

Inventor： Atsuhiro TSUYOSHI ,  Takashi OHTSUKA ,  Kenichi YOSHIDA

IPC: H05K1/18 ,  H05K3/30 ,  H05K3/46

CPC classification number: H05K1/188 ,  H05K3/305 ,  H05K3/4644 ,  H05K2201/0183

Abstract: An electronic component has: a conductor layer M1 formed on a substrate and including lower electrodes of a capacitor; a dielectric film covering the top and side surfaces of each of the lower electrodes; upper electrodes of the capacitor which are formed on the top surfaces of the respective lower electrodes through the dielectric film; and an adhesive film disposed between the dielectric film and the top and side surfaces of each of the lower electrodes. The adhesive film is thus disposed between the dielectric film and the top and side surfaces of each of the lower electrodes.

公开(公告)号：US20170027064A1

公开(公告)日：2017-01-26

申请号：US14807594

申请日：2015-07-23

Applicant: International Business Machines Corporation

Inventor： Sarah K. Czaplewski ,  Joseph Kuczynski ,  Jason T. Wertz ,  Jing Zhang

IPC: H05K3/28 ,  H05K3/00 ,  H05K3/46 ,  H05K1/02

CPC classification number: H05K3/28 ,  C09D163/00 ,  H05K1/02 ,  H05K1/11 ,  H05K3/0058 ,  H05K3/0079 ,  H05K3/282 ,  H05K3/284 ,  H05K3/288 ,  H05K3/4644 ,  H05K2201/0183 ,  H05K2201/09872 ,  H05K2203/1322

Abstract: In an example, a process for reversibly bonding a conformal coating to a dry film solder mask (DFSM) material is disclosed. The process includes applying a first conformal coating material to a DFSM material. The first conformal coating material includes a first functional group, and the DFSM material includes a second functional group that is different from the first functional group. The process also includes reversibly bonding the first conformal coating material to the DFSM material via a chemical reaction of the first functional group and the second functional group.

Abstract translation: 在一个实例中，公开了将保形涂层可逆地结合到干膜焊接掩模（DFSM）材料的方法。 该方法包括将第一保形涂层材料施加到DFSM材料。 第一保形涂层材料包括第一官能团，并且DFSM材料包括不同于第一官能团的第二官能团。 该方法还包括通过第一官能团和第二官能团的化学反应将第一共形涂层材料可逆地结合到DFSM材料。

公开(公告)号：US20140355218A1

公开(公告)日：2014-12-04

申请号：US14116642

申请日：2012-05-11

Applicant: Patrizio Vinciarelli ,  Michael B. LaFleur ,  Sean Timothy Fleming ,  Rudolph F. Mutter ,  Andrew T. D'Amico

Inventor： Patrizio Vinciarelli ,  Michael B. LaFleur ,  Sean Timothy Fleming ,  Rudolph F. Mutter ,  Andrew T. D'Amico

IPC: H05K3/28 ,  B29C45/14 ,  B29C45/00 ,  H05K1/18 ,  H05K1/11

CPC classification number: H05K3/284 ,  B29C45/0055 ,  B29C45/14639 ,  B29C2045/0058 ,  B29C2793/0009 ,  B29C2793/0027 ,  B29C2793/009 ,  H01R27/02 ,  H01R43/205 ,  H01R43/24 ,  H05K1/0209 ,  H05K1/111 ,  H05K1/186 ,  H05K3/0044 ,  H05K3/0052 ,  H05K3/007 ,  H05K5/064 ,  H05K5/065 ,  H05K7/209 ,  H05K2201/0183 ,  H05K2201/066 ,  H05K2201/10303 ,  H05K2201/10545 ,  H05K2203/1316 ,  H05K2203/1327 ,  H05K2203/167

Abstract: A method of encapsulating a panel of electronic components such as power converters reduces wasted printed circuit board area. The panel, which may include a plurality of components, may be cut into one or more individual pieces after encapsulation. The mold may be used to form part of the finished product. Interconnection features provided along boundaries of individual circuits are exposed during the singulation process providing electrical connections to the components without wasting valuable PCB surface area. The molds may include various internal features. Wide cuts may be made in the molds after encapsulation reducing thermal stresses. Blank mold panels may be machined to provide some or all of the above features in an on-demand manufacturing system. Connection adapters may be provided to use the modules in vertical or horizontal mounting positions in connector, through-hole, surface-mount solder variations.

Abstract translation: 封装诸如功率转换器之类的电子部件的面板的方法减少了浪费的印刷电路板面积。 可以包括多个部件的面板可以在封装之后切割成一个或多个单独的部件。 模具可用于形成成品的一部分。 在分离过程中，单独电路边界处提供的互连特征暴露于提供与组件的电连接，而不浪费有价值的PCB表面积。 模具可以包括各种内部特征。 封装后可以在模具中进行宽切削，减少热应力。 空白模具面板可以被加工以在按需制造系统中提供上述特征中的一些或全部。 可以提供连接适配器，以在连接器，通孔，表面贴装焊料变化中的垂直或水平安装位置使用模块。

公开(公告)号：US20230240020A1

公开(公告)日：2023-07-27

申请号：US17586212

申请日：2022-01-27

Applicant: XILINX, INC.

Inventor： Bhavesh PATEL

IPC: H05K3/34 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K3/3436 ,  H05K1/115 ,  H05K1/024 ,  H05K2201/10734 ,  H05K2201/0183

Abstract: An electronic device and methods for fabricating the same are disclosed herein that utilize a dam formed on a printed circuit board (PCB) that is positioned to substantially prevent edge bond material, utilized to secure a chip package to the PCB, from interfacing with the solder balls transmitting signals between the PCB and chip package.

公开(公告)号：US20230209730A1

公开(公告)日：2023-06-29

申请号：US18167908

申请日：2023-02-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Norikazu FUJII

IPC: H05K3/46 ,  H01P1/203 ,  H05K1/03

CPC classification number: H05K3/4697 ,  H01P1/203 ,  H05K1/03 ,  H05K2201/0183 ,  H01Q1/22

Abstract: A method includes after application of a bonding material, such as a metal paste, on a second dielectric substrate, a first dielectric substrate with a recess formed therein is laminated on the second dielectric substrate. Thereafter, the bonding material is sintered to form a cavity inside the dielectric substrate.

公开(公告)号：US09942989B2

公开(公告)日：2018-04-10

申请号：US14312222

申请日：2014-06-23

Applicant: ILLINOIS TOOL WORKS, INC.

Inventor： Hongchuan Liao ,  Chris Benson ,  Yong Liang ,  Tom Carlson

IPC: H05K7/00 ,  H05K1/18 ,  B32B27/08 ,  B32B27/20 ,  B32B27/32 ,  B32B27/34 ,  B32B27/36

CPC classification number: H05K1/185 ,  B32B27/08 ,  B32B27/20 ,  B32B27/32 ,  B32B27/34 ,  B32B27/36 ,  B32B27/365 ,  B32B2250/24 ,  B32B2250/40 ,  B32B2262/106 ,  B32B2264/02 ,  B32B2264/102 ,  B32B2264/105 ,  B32B2264/107 ,  B32B2264/108 ,  B32B2307/202 ,  B32B2307/206 ,  B32B2307/212 ,  B32B2307/302 ,  B32B2457/04 ,  H05K2201/0137 ,  H05K2201/0145 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/0183 ,  Y10T428/31507 ,  Y10T428/31681 ,  Y10T428/31692 ,  Y10T428/31721 ,  Y10T428/31725 ,  Y10T428/31728 ,  Y10T428/31736 ,  Y10T428/31757 ,  Y10T428/31786 ,  Y10T428/31797 ,  Y10T428/31913

Abstract: The present invention provides an insulation film and a method for making the insulation film, comprising a film upper layer and a film lower layer, wherein both of the film upper layer and film lower layer are made of a heat conduction plastics material, the heat conduction plastics material contains a heat conduction additive; and a film intermediate layer located between the film upper layer and the film lower layer. The film intermediate layer is made of a heat conduction plastics material, and the heat conduction plastics material contains a conductive additive An upper surface of the film intermediate layer is bound together with a lower surface of the film upper layer, and a lower surface of the film intermediate layer is bound together with an upper surface of the film lower layer.

公开(公告)号：US09775237B2

公开(公告)日：2017-09-26

申请号：US15153884

申请日：2016-05-13

Applicant: IBIDEN CO., LTD.

Inventor： Kosuke Ikeda

IPC: H05K1/09 ,  H05K1/02 ,  H05K1/11 ,  H05K1/03 ,  H05K3/46 ,  H05K3/40

CPC classification number: H05K1/0298 ,  H05K1/0204 ,  H05K1/0373 ,  H05K1/115 ,  H05K1/185 ,  H05K3/4038 ,  H05K3/4652 ,  H05K3/4661 ,  H05K3/4673 ,  H05K3/4697 ,  H05K2201/0183 ,  H05K2201/0195 ,  H05K2201/068 ,  H05K2201/10416

Abstract: A wiring substrate includes a core substrate, and a build-up layer including conductor layers and insulating layers alternately laminated on the substrate and via conductors formed in the insulating layers, each insulating layer having a coating layer and a support layer stacked on the coating layer such that the support layer has surface on which a conductor layer is laminated and the coating layer is covering a conductor layer, each via conductor connecting two conductor layers through an insulating layer. The coating layer has a thickness greater than that of the support layer and includes inorganic filler at content rate of 65 to 85% by mass, and the support layer includes inorganic filler at different content rate such that thermal expansion coefficient of the coating layer is smaller than that of the support layer and the coefficients of the coating and support layers have difference of 30 ppm/° C. or less.

公开(公告)号：US09655231B2

公开(公告)日：2017-05-16

申请号：US14275604

申请日：2014-05-12

Applicant: FUJITSU LIMITED

Inventor： Yasuo Hidaka

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/03 ,  H05K3/00

CPC classification number: H05K1/0245 ,  H01P3/08 ,  H05K1/024 ,  H05K1/0248 ,  H05K1/0313 ,  H05K1/0366 ,  H05K1/038 ,  H05K3/0091 ,  H05K3/10 ,  H05K3/4644 ,  H05K2201/0183 ,  H05K2201/07 ,  H05K2203/0195

Abstract: A circuit may be configured to reduce electrical signal degradation. The circuit may include a first trace and a second trace that may be broadside coupled between a first ground plane and a second ground plane. The first and second traces may be configured to carry first and second signals, respectively, of a differential signal. The circuit may also include a first dielectric material disposed between the first trace and the second trace. Further, the circuit may include a second dielectric material disposed between the first trace and the first ground plane and disposed between the second trace and the second ground plane. A difference between a first dielectric constant of the first dielectric material and a second dielectric constant of the second dielectric material may suppress a mode conversion of the differential signal from a differential mode to a common mode.

公开(公告)号：US20160353569A1

公开(公告)日：2016-12-01

申请号：US15158777

申请日：2016-05-19

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Jun FURUICHI ,  Noriyoshi SHIMIZU

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/11

CPC classification number: H05K1/0298 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H05K1/036 ,  H05K1/0366 ,  H05K1/115 ,  H05K3/0044 ,  H05K3/108 ,  H05K3/426 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/0183 ,  H05K2201/0191 ,  H05K2201/0376 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0979 ,  H05K2203/025

Abstract: A wiring substrate includes a core layer having a penetrating hole, a first insulating layer disposed on a first surface of the core layer and having a first opening at a position of the penetrating hole, the first insulating layer containing no filler, a penetrating electrode disposed in the penetrating hole and in the first opening, and a first wiring layer laminated both on the first insulating layer at a first surface thereof facing away from the core layer and on an end face of the penetrating electrode, wherein the first surface of the first insulating layer and the end face of the penetrating electrode are planarized.

Abstract translation: 布线基板包括具有穿透孔的芯层，设置在芯层的第一表面上的第一绝缘层，并且在穿透孔的位置处具有第一开口，第一绝缘层不包含填料，设置穿透电极 在所述贯通孔和所述第一开口中的第一表面以及在所述第一绝缘层上层叠的第一布线层，所述第一布线层在其背离所述芯层的第一表面和所述穿透电极的端面上， 绝缘层和穿透电极的端面被平坦化。

公开(公告)号：US20240174802A1

公开(公告)日：2024-05-30

申请号：US18508966

申请日：2023-11-14

Applicant: AGC Multi Material America, Inc.

Inventor： Preeya Kuray ,  Caleb Ancharski ,  Yoji Nakajima ,  Mark Derwin ,  Thomas Fitzgerald McCarthy, III ,  Takefumi Abe

IPC: C08G65/40 ,  C08G73/10 ,  C08J5/18 ,  C08K3/36 ,  C08K5/00 ,  C08K5/357 ,  C08K7/26 ,  H05K1/03

CPC classification number: C08G65/4037 ,  C08G73/10 ,  C08J5/18 ,  C08K3/36 ,  C08K5/0025 ,  C08K5/0066 ,  C08K5/357 ,  C08K7/26 ,  H05K1/0373 ,  C08J2371/12 ,  C08K2201/005 ,  H05K2201/0183

Abstract: This disclosure relates to a curable composition that includes at least one maleimide-containing compound or benzoxazine compound, at least one low dielectric loss polymer or a hydrogenated derivative thereof, at least one filler, and at least one radical initiator. This disclosure also relates to using the composition to form a film, a laminate, and/or a circuit board.