公开(公告)号：US20230156910A1

公开(公告)日：2023-05-18

申请号：US18098811

申请日：2023-01-19

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kosuke KIKUCHI ,  Kosuke NISHIO

IPC: H05K1/02 ,  H01P3/08 ,  H05K1/05

CPC classification number: H05K1/0237 ,  H01P3/08 ,  H05K1/05 ,  H05K2201/09209 ,  H05K2201/10015

Abstract: A circuit board includes a board body, a signal conductor, a power supply conductor, and a first reference conductor. The signal conductor is in the board body and a high frequency signal is transmitted through the signal conductor. The power supply conductor is in the board body and is connected to a power supply potential. The power supply conductor extends along at least a portion of the signal conductor. The first reference conductor is in the board body and is insulated from the signal conductor and the power supply conductor.

公开(公告)号：US20180070457A1

公开(公告)日：2018-03-08

申请号：US15664300

申请日：2017-07-31

Applicant: NITTO DENKO CORPORATION

Inventor： Takatoshi SAKAKURA ,  Tomoaki OKUNO ,  Takahiro TAKANO

IPC: H05K3/34 ,  H05K1/18 ,  H05K1/02

CPC classification number: H05K3/34 ,  H05K1/0296 ,  H05K1/18 ,  H05K2201/09209

Abstract: A suspension board with circuit includes a metal supporting layer, a base insulating layer disposed at one side in a thickness direction of the metal supporting layer, a conductive pattern including a wire disposed at one side in the thickness direction of the base insulating layer and a terminal exposed from the metal supporting layer and the base insulating layer when viewed from the other side in the thickness direction, a piezoelectric element disposed at the other side in the thickness direction with respect to the terminal and including an element terminal electrically connected to the terminal, and a solder layer disposed between the terminal and the element terminal. The solder layer has a solder composition containing Sn, Ag, and Cu, and the solder layer has a thickness in the thickness direction of 50 μm or less.

公开(公告)号：US20170303405A1

公开(公告)日：2017-10-19

申请号：US15486899

申请日：2017-04-13

Applicant: JX NIPPON MINING & METALS CORPORATION

Inventor： RYO FUKUCHI

IPC: H05K3/46 ,  B32B27/06 ,  B32B37/14 ,  H05K1/02 ,  B32B15/08 ,  H05K1/09 ,  B32B38/10 ,  H05K3/00 ,  H05K1/11

CPC classification number: H05K3/4652 ,  B32B15/08 ,  B32B27/06 ,  B32B37/14 ,  B32B38/10 ,  B32B2457/08 ,  H05K1/0237 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0026 ,  H05K3/022 ,  H05K3/384 ,  H05K2201/0355 ,  H05K2201/09209 ,  H05K2203/107

Abstract: To provide a copper foil that the transmission loss is favorably controlled even when the copper foil is used in a high-frequency circuit board and that adhesion to a resin is favorable.A copper foil including a roughened layer, and the roughened layer includes a primary particle layer, a surface roughness Ra of a surface on the side of the primary particle layer is 0.12 μm or less, and the average particle size of primary particles of the primary particle layer is 0.10 to 0.25 μm.

公开(公告)号：US20170042037A1

公开(公告)日：2017-02-09

申请号：US15220460

申请日：2016-07-27

Applicant: Rohm and Haas Electronic Materials LLC ,  Dow Global Technologies LLC

Inventor： Matthew Thorseth ,  Zuhra Niazimbetova ,  Yi Qin ,  Julia Woertink ,  Joanna Dziewiszek ,  Erik Reddington ,  Mark Lefebvre

IPC: H05K3/06 ,  C25D3/38 ,  H01L23/00 ,  C25D7/12 ,  H05K3/40 ,  H05K1/11 ,  G03F7/40 ,  C25D5/02

CPC classification number: H05K3/064 ,  C25D3/38 ,  C25D5/022 ,  C25D7/00 ,  C25D7/123 ,  G03F7/405 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/03462 ,  H01L2224/03472 ,  H01L2224/05015 ,  H01L2224/05147 ,  H01L2224/11 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13147 ,  H05K1/111 ,  H05K3/4007 ,  H05K2201/09209 ,  H01L2924/00012

Abstract: Electroplating methods enable the plating of photoresist defined features which have substantially uniform morphology. The electroplating methods include copper electroplating baths with reaction products of pyridyl alkylamines and bisepoxides to electroplate the photoresist defined features. Such features include pillars, bond pads and line space features.

Abstract translation: 电镀方法能够镀覆具有基本均匀形态的光致抗蚀剂限定特征。 电镀方法包括具有吡啶基烷基胺和二环氧化物的反应产物的电镀铜电镀以电镀所述光刻胶定义的特征。 这些特征包括支柱，接合垫和线空间特征。

公开(公告)号：US09078360B2

公开(公告)日：2015-07-07

申请号：US14012195

申请日：2013-08-28

Applicant: Ronald Steven Cok

Inventor： Ronald Steven Cok

IPC: H05K1/11 ,  H05K1/00 ,  H05K1/02 ,  H05K3/46 ,  H05K3/12 ,  H05K3/00

CPC classification number: H05K1/0274 ,  H05K1/0298 ,  H05K1/097 ,  H05K3/0041 ,  H05K3/12 ,  H05K3/1258 ,  H05K3/1275 ,  H05K3/1283 ,  H05K3/1291 ,  H05K3/465 ,  H05K3/4685 ,  H05K2201/09209 ,  H05K2201/09281 ,  H05K2201/0979 ,  H05K2201/09845 ,  H05K2203/0108

Abstract: An imprinted micro-structure includes a substrate having a first layer in relation thereto. First, second, and third micro-channels are imprinted in the first layer and have first, second, and third micro-wires respectively located therein. A second layer is adjacent to and in contact with the first layer. Imprinted first and second connecting micro-channels including first and second connecting micro-wires are in contact with the first and second micro-wires respectively and are isolated from the third micro-wire. A third layer is adjacent to and in contact with the second layer and has an imprinted bridge micro-channel with a bridge micro-wire contacting the first and second connecting micro-wires and separate from the third micro-wire so that the first and second micro-wires are electrically connected and electrically isolated from the third micro-wire.

Abstract translation: 压印的微结构包括具有与之相关的第一层的衬底。 第一，第二和第三微通道印在第一层中，并且分别位于其中的第一，第二和第三微细线。 第二层与第一层相邻并与第一层接触。 包括第一和第二连接微线的印刷的第一和第二连接微通道分别与第一和第二微线接触并与第三微线隔离。 第三层与第二层相邻并与第二层接触，并且具有印刷桥微通道，桥接微线与第一和第二连接微线接触并与第三微线分离，使得第一和第二 微线电连接并与第三微线电隔离。

公开(公告)号：US09818682B2

公开(公告)日：2017-11-14

申请号：US14558864

申请日：2014-12-03

Applicant: International Business Machines Corporation

Inventor： Edmund Blackshear ,  Shidong Li

IPC: B32B3/24 ,  B32B5/16 ,  B32B7/02 ,  B32B15/092 ,  B32B27/04 ,  B32B27/38 ,  B32B37/02 ,  H01L23/48 ,  H01L23/498 ,  B32B3/26 ,  B32B38/00 ,  B32B37/18 ,  H05K1/02 ,  H05K1/03 ,  H05K3/00 ,  H05K13/00 ,  H01L21/48 ,  B32B15/20 ,  B32B27/20 ,  B32B3/08 ,  B32B3/10

CPC classification number: H01L23/49833 ,  B32B3/08 ,  B32B3/10 ,  B32B3/266 ,  B32B5/16 ,  B32B7/02 ,  B32B15/092 ,  B32B15/20 ,  B32B27/04 ,  B32B27/20 ,  B32B27/38 ,  B32B37/02 ,  B32B37/182 ,  B32B38/0004 ,  B32B2250/05 ,  B32B2250/40 ,  B32B2260/046 ,  B32B2262/101 ,  B32B2264/10 ,  B32B2264/101 ,  B32B2307/202 ,  B32B2307/204 ,  B32B2307/734 ,  B32B2363/00 ,  B32B2457/00 ,  B32B2457/14 ,  H01L21/4803 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2924/0002 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K2201/0137 ,  H05K2201/0191 ,  H05K2201/0206 ,  H05K2201/0209 ,  H05K2201/09136 ,  H05K2201/09209 ,  H05K2201/0929 ,  H05K2203/06 ,  H05K2203/061 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T428/24298 ,  Y10T428/24314 ,  Y10T428/24322 ,  Y10T428/24331 ,  Y10T428/25 ,  H01L2924/00

Abstract: A laminate substrate for receiving a semiconductor chip. Included are laminate layers stacked to form the laminate substrate, each laminate layer includes a core that includes particle-filled epoxy and a metallic layer on the core. At least one laminate layer has a radial cut through the metallic layer, the radial cut extending from a periphery of the at least one laminate layer towards a center of the at least one laminate layer. The radial cut cuts only through the metallic layer and does not cut through the core.

公开(公告)号：US20170037527A1

公开(公告)日：2017-02-09

申请号：US15220472

申请日：2016-07-27

Applicant: Rohm and Haas Electronic Materials LLC ,  Dow Global Technologies LLC

Inventor： Matthew Thorseth ,  Zuhra Niazimbetova ,  Yi Qin ,  Julia Woertink ,  Joanna Dziewiszek ,  Erik Reddington ,  Mark Lefebvre

IPC: C25D3/38 ,  C25D7/12 ,  H01L23/00 ,  H05K3/40 ,  H05K1/11 ,  C25D5/02 ,  H05K3/06

CPC classification number: C25D3/38 ,  C25D5/022 ,  C25D7/00 ,  C25D7/123 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/03462 ,  H01L2224/03472 ,  H01L2224/05015 ,  H01L2224/11 ,  H01L2224/11472 ,  H01L2224/13014 ,  H01L2224/13147 ,  H05K1/111 ,  H05K3/064 ,  H05K3/4007 ,  H05K2201/09209 ,  H01L2924/00012

Abstract: Electroplating methods enable the plating of photoresist defined features which have substantially uniform morphology. The electroplating methods include copper electroplating baths with reaction products of α-amino acids and bisepoxides to electroplate the photoresist defined features. Such features include pillars, bond pads and line space features.

Abstract translation: 电镀方法能够镀覆具有基本均匀形态的光致抗蚀剂限定特征。 电镀方法包括具有α-氨基酸和双环氧化物的反应产物的电镀铜电镀以电镀所述光致抗蚀剂的特征。 这些特征包括支柱，接合垫和线空间特征。

公开(公告)号：US20170037526A1

公开(公告)日：2017-02-09

申请号：US15220467

申请日：2016-07-27

Applicant: Rohm and Haas Electronic Materials LLC ,  Dow Global Technologies LLC

Inventor： Matthew Thorseth ,  Zuhra Niazimbetova ,  Yi Qin ,  Julia Woertink ,  Joanna Dziewiszek ,  Erik Reddington ,  Mark Lefebvre

IPC: C25D3/38 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H05K1/11 ,  C25D5/02 ,  G03F7/40 ,  H05K3/06 ,  H05K3/40 ,  H01L23/00 ,  C25D7/12

CPC classification number: C25D3/38 ,  C25D5/022 ,  C25D7/00 ,  C25D7/12 ,  C25D7/123 ,  G03F7/405 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53228 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/05147 ,  H01L2224/11 ,  H01L2224/11462 ,  H01L2224/13147 ,  H05K1/11 ,  H05K3/064 ,  H05K3/4007 ,  H05K2201/09209 ,  H01L2924/00012

Abstract: Electroplating methods enable the plating of photoresist defined features which have substantially uniform morphology. The electroplating methods include copper electroplating baths with reaction products of imidazole and bisepoxides to electroplate the photoresist defined features. Such features include pillars, bond pads and line space features.

Abstract translation: 电镀方法能够镀覆具有基本均匀形态的光致抗蚀剂限定特征。 电镀方法包括具有咪唑和双环氧化物的反应产物的电镀铜电镀以电镀光刻胶定义的特征。 这些特征包括支柱，接合垫和线空间特征。

公开(公告)号：US20150062834A1

公开(公告)日：2015-03-05

申请号：US14469675

申请日：2014-08-27

Applicant: YAZAKI CORPORATION

Inventor： Takanori KITAJO ,  Masaki SUGIYAMA ,  Masayuki NAOHARA

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/111 ,  H01R12/526 ,  H01R29/00 ,  H05K1/029 ,  H05K1/14 ,  H05K1/182 ,  H05K3/222 ,  H05K2201/042 ,  H05K2201/09209 ,  H05K2201/10363 ,  H05K2201/10954

Abstract: A jumper module mounting circuit board includes: a circuit board; and a jumper module having an insulator main body provided with conductive electrical connection parts for connecting between connection patterns so as to provide electrical continuity therebetween by connecting each of contact parts on both ends of the conductive electrical connection parts to the connection patterns which are formed to be spaced apart from each other on the circuit board. The jumper module is mounted onto the circuit board so as to connect between the contact parts and the connection patterns that are formed to be spaced apart from each other. The circuit board includes a connection pattern concentrated section that is formed by concentrating the connection patterns depending on a plurality of wiring specifications at a mount position of the jumper module.

Abstract translation: 跳线模块安装电路板包括：电路板; 以及跳线模块，其具有绝缘体主体，该绝缘体主体设置有用于连接连接图案之间的导电电连接部件，以便通过将导电电连接部件的两端上的每个接触部分连接到形成为 在电路板上彼此间隔开。 跳线模块安装在电路板上，以便在接触部分和形成为彼此间隔开的连接图案之间连接。 电路板包括通过在跳线模块的安装位置根据多个布线规格聚集连接图案形成的连接图案集中部分。

公开(公告)号：US20150060395A1

公开(公告)日：2015-03-05

申请号：US14012240

申请日：2013-08-28

Applicant: RONALD STEVEN COK

Inventor： RONALD STEVEN COK

IPC: H05K3/12

CPC classification number: H05K1/0274 ,  H05K1/0298 ,  H05K1/097 ,  H05K3/0041 ,  H05K3/12 ,  H05K3/1258 ,  H05K3/1275 ,  H05K3/1283 ,  H05K3/1291 ,  H05K3/465 ,  H05K3/4685 ,  H05K2201/09209 ,  H05K2201/09281 ,  H05K2201/0979 ,  H05K2201/09845 ,  H05K2203/0108

Abstract: A method of making an imprinted micro-wire structure includes providing a substrate having an edge area and a central area separate from the edge area and providing a first stamp and a multi-level second stamp. A curable bottom layer and multi-layer are provided on the substrate. A bottom-layer micro-channel is imprinted in the bottom layer. A multi-layer micro-channel and a top-layer micro-channel are imprinted in the multi-layer. Micro-wires are formed in each micro-channel. The bottom-layer micro-wire extends from the central area into the edge area. The multi-layer micro-wire contacts the bottom-layer micro-wire in the edge area. The top-layer micro-wire is over the central area and is separate from the multi-layer micro-wire and the bottom-layer micro-channel. The bottom-layer micro-wire is electrically connected to the multi-layer micro-wire and is electrically isolated from the top-layer micro-wire.

Abstract translation: 制造压印微线结构的方法包括提供具有与边缘区域分离的边缘区域和中心区域的基板，并提供第一印模和多级第二印模。 在基板上设置有可固化的底层和多层。 底层微通道印在底层中。 多层微通道和顶层微通道印在多层中。 微线形成在每个微通道中。 底层微线从中心区域延伸到边缘区域。 多层微线接触边缘区域的底层微线。 顶层微线在中心区域之上，与多层微线和底层微通道分离。 底层微线电连接到多层微线，并与顶层微线电隔离。