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公开(公告)号：KR100943861B1
公开(公告)日：2010-02-24
申请号：KR1020080055220
申请日：2008-06-12
Applicant: 에스케이하이닉스 주식회사 , 재단법인서울대학교산학협력재단
IPC: G11C11/4093 , G11C11/4096
CPC classification number: G06F13/4086
Abstract: 1. 청구범위에 기재된 발명이 속하는 기술 분야
본 발명은 양방향 멀티 드롭 구조의 버스 시스템, 그를 이용한 메모리 시스템 및 메모리 모듈에 관한 것임.
2. 발명이 해결하려고 하는 기술적 과제
본 발명은 상호 신호 간섭을 유발하는 반사파가 존재하지 않는 양방향 멀티 드롭 구조의 버스 시스템, 그를 이용한 메모리 시스템 및 메모리 모듈을 제공함.
3. 발명의 해결방법의 요지
본 발명은 [K+1]개의 스터브; 상기 스터브 각각의 일단에 메모리 모듈이 장착되는 커넥터; 상기 커넥터에 연결되는 직렬 부하; 및 상기 스터브의 버스 선로의 특성 임피던스에 연결되는 직렬 부하를 포함함.
4. 발명의 중요한 용도
본 발명은 메모리 시스템에 이용됨.
버스, 메모리 시스템, 임피던스 매칭, 반사파-
公开(公告)号：KR1020090129118A
公开(公告)日：2009-12-16
申请号：KR1020080055220
申请日：2008-06-12
Applicant: 에스케이하이닉스 주식회사 , 재단법인서울대학교산학협력재단
IPC: G11C11/4093 , G11C11/4096
CPC classification number: G06F13/4086 , G11C11/4093 , G11C7/1048 , G11C11/4096 , H03K19/017545
Abstract: PURPOSE: An impedance-matched bidirectional multi-drop bus system, and a memory system and a memory module using the same are provided to suppress the generation of a reflected wave which causes ISI(Inter Symbol Interference), thereby secure bandwidth required in a next memory system. CONSTITUTION: A bidirectional multi-drop bus system(801) of a memory system(800) comprises a connector(831[0]~831[k]) which is formed one end of each of [K+1] stubs(811[0]~811[k]). Each of [K+1] memory modules(803[0]~803[K]) is installed to each connector. Each of memory chips(813[0]~813[K]) is installed in each of the [K+1]memory modules. A memory controller(805) is connected to one end of the bus system. ODT(On Die Termination) is performed for the memory chips and the memory controller with ODT load Rodt.
Abstract translation: 目的：提供阻抗匹配的双向多点总线系统以及使用其的存储器系统和存储器模块以抑制产生引起ISI（符号间干扰）的反射波，从而确保下一个所需的带宽 内存系统 构成：存储器系统（800）的双向多点总线系统（801）包括形成[K + 1]个存根（811 [8] [8]]的一端的连接器（831 [0]〜831 [k] 0]〜811 [K]）。 [K + 1]个存储器模块（803 [0]〜803 [K]）安装到每个连接器。 每个存储器芯片（813 [0]〜813 [K]）被安装在每个[K + 1]个存储器模块中。 存储器控制器（805）连接到总线系统的一端。 使用ODT负载Rodt对存储器芯片和存储器控制器执行ODT（On Die Termination）。
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公开(公告)号：KR100684115B1
公开(公告)日：2007-02-16
申请号：KR1020060010766
申请日：2006-02-03
Applicant: 재단법인서울대학교산학협력재단 , (주)글로넷시스템즈
IPC: G11C15/00
Abstract: A range-matching cell and a CAM(Content Addressable Memories) using the same are provided to use a memory more efficiently, by providing an amplitude comparison operator in performing range searching using amplitude comparison. A bit line pair comprises a bit line(BL) and an inverted bit line(/BL) for transmitting data. A memory cell(100) is connected to a word line and the bit line pair, and stores the data transmitted through the bit line pair when the word line is enabled. A search line pair comprises a search line(SL) and an inverted search line(/SL) for transmitting search data. A first comparison part(110) is connected to the memory cell, the search line pair and a match line(ML), and turns on or off a first switching device serially connected to the match line in response to the data stored in the memory cell and the search data transmitted through the search line. A second comparison part(120) connects the match line to a ground voltage or a predetermined voltage in response to the search data transmitted through the search line and the stored operator data when the first switching device is turned off.
Abstract translation: 通过在使用幅度比较执行范围搜索时提供幅度比较运算器，提供范围匹配单元和使用该单元的CAM（内容可寻址存储器）以更高效地使用存储器。 位线对包括用于传输数据的位线（BL）和反转位线（/ BL）。 存储器单元（100）连接到字线和位线对，并且当字线被使能时存储通过位线对传输的数据。 搜索线对包括用于发送搜索数据的搜索线（SL）和反向搜索线（SL）。 第一比较部分（110）连接到存储单元，搜索线对和匹配线（ML），并且响应于存储在存储器中的数据而打开或关闭串行连接到匹配线的第一开关装置 小区和通过搜索线传输的搜索数据。 当第一开关装置断开时，第二比较部分（120）响应于通过搜索线传输的搜索数据和存储的操作者数据将匹配线连接到地电压或预定电压。
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公开(公告)号：KR1020100005329A
公开(公告)日：2010-01-15
申请号：KR1020080065318
申请日：2008-07-07
Applicant: 지씨티 세미컨덕터 인코포레이티드 , 재단법인서울대학교산학협력재단
CPC classification number: H03M1/668 , H03M1/70 , H03M2201/6121 , H03M2201/6309
Abstract: PURPOSE: A digital to analog converter for a continuous time sigma delta modulator is provided to improve performance of the converter by controlling a duty ratio of a clock signal. CONSTITUTION: An adding unit(110) adds up a continuous time analog input signal and an analog signal outputted from a digital to analog converter(140). A loop filter(120) includes at least one integrator to perform an integral operation. The integrator is comprised of an operational amplifier and a capacitor. A quantizer(130) performs the quantization operation based on the signal outputted from the loop filter and outputs the digital signal. The digital signal is comprised of one bit or plural bits. The digital to analog converter outputs the analog signal based on the digital signal outputted from the quantizer.
Abstract translation: 目的：提供用于连续时间Σ-Δ调制器的数模转换器，用于通过控制时钟信号的占空比来提高转换器的性能。 构成：添加单元（110）将从模拟转换器（140）输出的连续时间模拟输入信号和模拟信号相加。 环路滤波器（120）包括至少一个积分器以执行积分运算。 积分器由运算放大器和电容器组成。 量化器（130）基于从环路滤波器输出的信号进行量化操作并输出数字信号。 数字信号由一位或多位构成。 数模转换器根据从量化器输出的数字信号输出模拟信号。
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公开(公告)号：KR100925397B1
公开(公告)日：2009-11-09
申请号：KR1020070092618
申请日：2007-09-12
Applicant: 지씨티 세미컨덕터 인코포레이티드 , 재단법인서울대학교산학협력재단
IPC: H03M3/02
Abstract: 연속 시간 시그마 델타 아날로그-디지털 컨버터를 위한 루프 필터는 시그마 델타 아날로그-디지털 컨버터(ADC, Analog to Digital Converter)로부터 출력된 디지털 출력 신호의 적어도 일부를 표현하는 입력 신호를 입력받는 입력단, 및 상기 입력단과 연결되고, 전력 이득을 제공하기 위한 M개의 능동 소자들 및 상기 능동 소자들 각각으로부터 출력된 신호 모두를 표현하는 출력 신호를 출력하는 출력단을 포함하며, N(N>M)차 적분을 수행하는 아날로그 능동 필터를 포함한다. 따라서 NTF(Noise Transfer Function) 특성이 개선될 수 있다.
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Patent Agency Ranking
公开(公告)号：KR1020080107829A
公开(公告)日：2008-12-11
申请号：KR1020070056120
申请日：2007-06-08
Applicant: 재단법인서울대학교산학협력재단 , 주식회사 시너칩
IPC: H03M1/66
CPC classification number: H03M1/662 , H03M2201/16 , H03M2201/311 , H03M2201/3157 , H03M2201/62
Abstract: A segmented digital to analog converter is provided to perform the miniaturization by reducing the number of the switches used in a coarse digital to analog converter. A segmented DAC(Digital to Analog Converter)(100) includes a first digital to analog converter, and a second digital-to-analog converter. The first digital to analog converter includes a first output terminal and a second output terminal. The first output terminal outputs a first coarse voltage. The second output terminal outputs a second coarse voltage. The second digital to analog converter outputs a minute voltage obtained by interpolating the first coarse voltage and the second coarse voltage. The first digital to analog converter includes a register string(110), and a first switch unit(120). The register string includes a plurality of resisters which are serially connected. The register string outputs a plurality of reference voltages. The first switch unit outputs two consecutive reference voltages selected among the plurality of the reference voltages as the first and second coarse voltages. The first coarse voltage is selected among odd-number reference voltages among the plurality of reference voltages. The second coarse voltage is selected among even-number reference voltages among the plurality of reference voltages.
Abstract translation: 提供分段数模转换器以通过减少粗略数模转换器中使用的开关数量来执行小型化。 分段DAC（数模转换器）（100）包括第一数模转换器和第二数/模转换器。 第一数模转换器包括第一输出端和第二输出端。 第一输出端输出第一粗电压。 第二输出端输出第二粗电压。 第二数模转换器输出通过内插第一粗电压和第二粗电压而获得的微小电压。 第一数模转换器包括寄存器串（110）和第一开关单元（120）。 寄存器串包括串联连接的多个电阻。 寄存器串输出多个参考电压。 第一开关单元输出在多个参考电压中选择的两个连续的参考电压作为第一和第二粗略电压。 第一粗略电压在多个参考电压中的奇数参考电压中选择。 第二粗电压在多个参考电压中的偶数参考电压中选择。
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公开(公告)号：KR1020110014643A
公开(公告)日：2011-02-11
申请号：KR1020107027916
申请日：2008-05-14
Applicant: 재단법인서울대학교산학협력재단
CPC classification number: H03L7/0995 , H03K3/0322 , H03K3/35613 , H03K2005/0013 , H03L1/00 , H03L7/0998 , H03L7/18 , H03L2207/50
Abstract: PURPOSE: A method for eliminating jitter and a digital control oscillating circuit using the same are provided to oscillate a clock in a pre-set frequency without jitter noises by constantly maintaining wave delaying time. CONSTITUTION: The output of N-type metal oxide semiconductor(MOS) drivers(160, 170) of a differential amplifier is in connection with the gate terminal of an NMOS transistor. The output of PMOS load transistors(180, 190) is in connection with the gate of a PMOS transistor. A pseudo-differential amplifying circuit is composed of the NMOS transistor and the PMOS transistor. The output of the pseudo-differential amplifying circuit is in connection with the output of an inverter terminal composed of transistors(120, 130).
Abstract translation: 目的：提供消除抖动的方法和使用该方法的数字控制振荡电路，以通过不断维持波延迟时间来振荡具有预设频率的时钟，而不产生抖动噪声。 构成：差分放大器的N型金属氧化物半导体（MOS）驱动器（160,170）的输出与NMOS晶体管的栅极端子连接。 PMOS负载晶体管（180,190）的输出与PMOS晶体管的栅极连接。 伪差分放大电路由NMOS晶体管和PMOS晶体管构成。 伪差分放大电路的输出与由晶体管（120,130）构成的反相器端子的输出相连。
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公开(公告)号：KR100968489B1
公开(公告)日：2010-07-07
申请号：KR1020080064927
申请日：2008-07-04
Applicant: 재단법인서울대학교산학협력재단
Abstract: 본 발명은 데이터 저장 입자 및 데이터 저장 입자를 포함하는 데이터 전송 시스템에 관한 것으로, 데이터 저장 입자는 수신 신호로부터 인코딩된(encoded) 데이터를 구하는 수신부, 수신부로부터 전달된 인코딩된 데이터를 비휘발성 메모리에 쓰고 비휘발성 메모리에 써진 인코딩된 데이터를 읽는 제어부 및 비휘발성 메모리로부터 읽어진 인코딩된 데이터에 대응하는 송신 신호를 전송하는 송신부를 구비함으로써 데이터 저장 입자의 구성을 단순하게 구현할 수 있으며, 데이터 저장 입자에서 소비되는 전력을 줄일 수 있다.
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公开(公告)号：KR1020090131233A
公开(公告)日：2009-12-28
申请号：KR1020080064927
申请日：2008-07-04
Applicant: 재단법인서울대학교산학협력재단
CPC classification number: G06K17/0022 , G06F12/0238 , G06K19/0704 , G06K19/0728
Abstract: PURPOSE: A data storing particle and a data transmission system are provided to write encoded data on a nonvolatile memory and to read the encoded data, thereby simply realizing a configuration of the data storing particle. CONSTITUTION: A receiving unit(120) obtains encoded data from a received signal. A control unit(140) writes the encoded data delivered from the receiving unit on a nonvolatile memory(150). The control unit reads the encoded data written on the nonvolatile memory. A transmitting unit(160) transmits a transmission signal corresponding to the encoded data read from the nonvolatile memory. The receiving signal is wirelessly received, and the transmission signal is wirelessly transmitted.
Abstract translation: 目的：提供数据存储粒子和数据传输系统，以将编码数据写入非易失性存储器并读取编码数据，从而简单地实现数据存储粒子的配置。 构成：接收单元（120）从接收到的信号中获得编码数据。 控制单元（140）将从接收单元发送的编码数据写入非易失性存储器（150）。 控制单元读取写在非易失性存储器上的编码数据。 发送单元（160）发送与从非易失性存储器读取的编码数据相对应的发送信号。 无线地接收接收信号，无线发送发送信号。
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公开(公告)号：KR1020090027416A
公开(公告)日：2009-03-17
申请号：KR1020070092618
申请日：2007-09-12
Applicant: 지씨티 세미컨덕터 인코포레이티드 , 재단법인서울대학교산학협력재단
IPC: H03M3/02
CPC classification number: H03M3/494 , H03M1/12 , H03M3/394 , H03M2201/61 , H03M2201/646
Abstract: A loop filter for a continuous time sigma delta analog to digital converter is provided to improve a NTF(Noise Transfer Function) property of a continuous time sigma delta analog to digital converter by using a sallen and key filter element. A loop filter includes an input terminal(1110) and an analog active filter(1120). An input signal(X2(t)) is inputted in the input terminal, and indicates at least a part of a digital output signal(y(n)) outputted from a sigma delta analog to digital converter. The analog active filter is connected to the input terminal, and includes M active devices(1122, 1124, 1126) and an output terminal(1128). M active devices provide a power gain. An output signal(I5(t)) is outputted from the output terminal, and indicates a total signal outputted from M active devices. The analog active filter performs N(N>M) integration.
Abstract translation: 提供了一种用于连续时间Σ-Δ模数转换器的环路滤波器，以通过使用sallen和键滤波器元件来提高连续时间Σ-Δ模数转换器的NTF（噪声传递函数）特性。 环路滤波器包括输入端子（1110）和模拟有源滤波器（1120）。 输入信号（X2（t））被输入到输入端子，并且指示从Σ-Δ模数转换器输出的数字输出信号（y（n））的至少一部分。 模拟有源滤波器连接到输入端，并且包括M个有源器件（1122,1124,1126）和一个输出端子（1128）。 M个有源器件提供功率增益。 从输出端输出输出信号（I5（t）），表示从M个有源装置输出的总信号。 模拟有源滤波器进行N（N> M）整合。
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