公开(公告)号：WO2015055376A1

公开(公告)日：2015-04-23

申请号：PCT/EP2014/069994

申请日：2014-09-19

Applicant: ABB TECHNOLOGY AG

Inventor： COTTET, Didier ,  STIASNY, Thomas

IPC: H01L25/18 ,  H03K17/12 ,  H03K17/51

CPC classification number: H01L25/18 ,  H01L2924/0002 ,  H03K17/732 ,  H01L2924/00

Abstract: A module (10) for a semiconductor switch (16) comprises a circuit board (12), a semiconductor switch (16) carried by the circuit board (12), wherein the semiconductor switch (16) has a disc-like shape with two opposite faces (18) and a border (20), which provides a gate contact area (24) to a gate of the semiconductor switch (16), a gate unit (22) with circuitry carried by the circuit board (12), wherein the gate unit (22) is adapted for controlling the gate of the semiconductor switch (16) with at least one output (38) to be connected to the gate, and a gate layer (26) provided on the circuit board (12) and electrically interconnecting the gate contact area (24) on the border (20) of the semiconductor switch (16) with the at least one output (38) of the gate unit (22). The gate layer (26) is divided in at least two slices (26a, 26b) laying side by side on the circuit board (12) and providing at least two paths for an electrical current between the gate contact area (24) and the gate unit (22).The at least two slices (26a, 26b) contact the at least one output (38) of the gate unit (22) with lateral contact sections (32a, 32b) that are aligned on the circuit board (12) on one side of the semiconductor switch (16).Moreover, a method for switching a semiconductor switch (16) of a module (10)is mentioned.

Abstract translation: 用于半导体开关（16）的模块（10）包括电路板（12），由电路板（12）承载的半导体开关（16），其中半导体开关（16）具有盘形形状，具有两个 相对面（18）和边界（20），其向半导体开关（16）的栅极提供栅极接触区域（24），具有由电路板（12）承载的电路的栅极单元（22），其中 门单元（22）适于用至少一个要连接到栅极的输出端（38）来控制半导体开关（16）的栅极，以及设置在电路板（12）上的栅极层（26）和 将半导体开关（16）的边界（20）上的栅极接触区域（24）与栅极单元（22）的至少一个输出端（38）电连接。 栅极层（26）被划分成在电路板（12）上并排布置的至少两个切片（26a，26b），并且在栅极接触区域（24）和栅极（24）之间提供用于电流的至少两条路径 所述至少两个切片（26a，26b）与所述门单元（22）的所述至少一个输出（38）接触，所述至少一个输出（38）与所述电路板（12）上对准的侧向接触部分（32a，32b） 在半导体开关（16）的一侧上，还提及了用于切换模块（10）的半导体开关（16）的方法。

公开(公告)号：WO2013056933A3

公开(公告)日：2013-04-25

申请号：PCT/EP2012/068205

申请日：2012-09-17

Applicant: ABB TECHNOLOGY AG ,  APELDOORN, Oscar ,  COTTET, Didier ,  SCHÜTZ, Gregor ,  CIMINO, Mikael

Inventor： APELDOORN, Oscar ,  COTTET, Didier ,  SCHÜTZ, Gregor ,  CIMINO, Mikael

IPC: H02J9/06 ,  H02M1/08 ,  H02J9/08 ,  H05K7/20

Abstract: A power electronics device 10 for processing an electrical current comprises a cooling fluid stream generation device 24 at a first potential for generating a cooling fluid stream 18, an electronic module 12 at a second potential and an auxiliary power supply device 26 at the second potential for supplying the electronic module 12 with auxiliary electrical power. The auxiliary power supply device 26 comprises a turbine 30for receiving the cooling fluid stream 18 and for generating auxiliary electrical power from the cooling fluid stream 18.

公开(公告)号：WO2015176985A1

公开(公告)日：2015-11-26

申请号：PCT/EP2015/060351

申请日：2015-05-11

Applicant: ABB TECHNOLOGY AG

Inventor： COTTET, Didier ,  CAVALLINI, Giacomo ,  HARTMANN, Samuel ,  KICIN, Slavo

IPC: H01L23/64 ,  H01L23/373 ,  H01L25/07

CPC classification number: H01L25/072 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/5385 ,  H01L23/645 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2924/19107

Abstract: A semiconductor half-bridge module (10) comprises a first substrate (28) with at least one metallization layer (34) on at least one side, a first line (38a) of semiconductor chips (24a, 24b) electrically and mechanically bonded to a metallization layer (34) of the first substrate (28), a second line (38b) of semiconductor chips (24a, 24b) electrically and mechanically bonded to a metallization layer (34) of the first substrate (28), and a second substrate (30) mechanically bonded with one side to a metallization layer (34) of the first substrate (28) between the first line (38a) and the second line (38b), the second substrate (30) having at least one metallization layer (34e) on a second opposite side providing a DC contact (22) of the module (10). An electrical contact (26) of the semiconductor chips (24a, 24b) of the first line (38a) and/or of the second line (38b) is directly electrically connected to a metallization layer of the second substrate (30). The semiconductor chips (24a, 24b) form a first switch (14) and a second switch (16) of a half-bridge (12), such that a current between the first switch (14) and the second switch (16) flows below the second substrate (30).

Abstract translation: 半导体半桥模块（10）包括在至少一侧具有至少一个金属化层（34）的第一衬底（28），半导体芯片（24a，24b）的第一线（38a），电和机械地结合到 所述第一基板（28）的金属化层（34），与所述第一基板（28）的金属化层（34）电气和机械结合的半导体芯片（24a，24b）的第二线（38b） 衬底（30）在第一线（38a）和第二线（38b）之间与一侧机械地结合到第一衬底（28）的金属化层（34），第二衬底（30）具有至少一个金属化层 （34e）在提供模块（10）的DC触点（22）的第二相对侧上。 第一线（38a）和/或第二线（38b）的半导体芯片（24a，24b）的电触点（26）直接电连接到第二基板（30）的金属化层。 半导体芯片（24a，24b）形成半桥（12）的第一开关（14）和第二开关（16），使得第一开关（14）和第二开关（16）之间的电流流过 在第二基板（30）的下方。

公开(公告)号：WO2015132128A1

公开(公告)日：2015-09-11

申请号：PCT/EP2015/054044

申请日：2015-02-26

Applicant: ABB TECHNOLOGY AG

Inventor： GRADINGER, Thomas ,  DONZEL, Lise ,  COTTET, Didier ,  GREUTER, Felix

IPC: H05K7/14

CPC classification number: H05K7/1432

Abstract: The present invention relates to an Enclosure for power electronic components, comprising: an enclosure wall (22) comprising an insulating material, a first conductive layer (24) covering a portion of an inner face (26) of the enclosure wall (22), and a second conductive layer (28) covering at least a portion of an outer face (30) of the enclosure wall (22), wherein the first (24) and the second (28) conductive layers are electrically insulated from each other by the enclosure wall (22) and are capable of exhibiting a different electrical potential, and wherein at least a portion of the inner face (26) of the enclosure wall (22) not being covered with a conductive layer (24, 28) and abutting the portion being covered by the conductive layer (24, 28) is covered by a resistive material layer (34). Such an enclosure (20) provides an improved insulation, especially with regard to field grading.

Abstract translation: 本发明涉及一种用于电力电子部件的外壳，包括：包括绝缘材料的外壳壁（22），覆盖外壳壁（22）的内表面（26）的一部分的第一导电层（24） 以及覆盖所述封闭壁（22）的外表面（30）的至少一部分的第二导电层（28），其中所述第一导电层（24）和所述第二导电层（28）彼此电绝缘 壳体壁（22）并且能够呈现不同的电势，并且其中外壳壁（22）的内表面（26）的至少一部分不被导电层（24,28）覆盖并且邻接 由导电层（24,28）覆盖的部分被电阻材料层（34）覆盖。 这种外壳（20）提供了改进的绝缘，特别是在现场分级方面。

公开(公告)号：WO2013004289A1

公开(公告)日：2013-01-10

申请号：PCT/EP2011/061215

申请日：2011-07-04

Applicant: ABB TECHNOLOGY AG ,  HÄFNER, Jürgen ,  COTTET, Didier ,  NISTOR, Iulian ,  STORASTA, Liutauras ,  RAHIMO, Munaf ,  SCHULZ, Nicola ,  STRASSEL, Thorsten ,  SCHNELL, Raffael

Inventor： HÄFNER, Jürgen ,  COTTET, Didier ,  NISTOR, Iulian ,  STORASTA, Liutauras ,  RAHIMO, Munaf ,  SCHULZ, Nicola ,  STRASSEL, Thorsten ,  SCHNELL, Raffael

IPC: H02H7/12 ,  H02M7/5387 ,  H03K17/08

CPC classification number: H02H7/12 ,  H02M1/088 ,  H02M2001/325

Abstract: A method for simplifying short circuit failure mode (SCFM) transitions in a power electronics module. The method includes keeping at least one switch (101, 102, 103, 104) in closed position by means of a signal (109) supplied by a gate unit (110). Upon a failure of a first semiconductor chip (105) during which the failed chip enters an SCFM, the switch (102, 103, 104) is opened, wherein the gates of the second semiconductor chips (106, 107, 108) become floating. Thereby the blocking voltage of the semiconductor chips is reduced.

Abstract translation: 一种用于简化电力电子模块中的短路故障模式（SCFM）转换的方法。 该方法包括通过由门单元（110）提供的信号（109）将至少一个开关（101,102,103,104）保持在闭合位置。 在故障芯片进入SCFM期间的第一半导体芯片（105）发生故障时，开关（102,103,104）被打开，其中第二半导体芯片（106,107,108）的栅极变为浮置。 由此，半导体芯片的阻断电压降低。

公开(公告)号：WO2016165843A1

公开(公告)日：2016-10-20

申请号：PCT/EP2016/052161

申请日：2016-02-02

Applicant: ABB TECHNOLOGY AG

Inventor： SCHUDERER, Jürgen ,  MOHN, Fabian ,  COTTET, Didier ,  TRAUB, Felix ,  KEARNEY, David

IPC: H01L23/473

CPC classification number: H01L23/473 ,  H01L23/3142 ,  H01L23/49844 ,  H01L24/48 ,  H01L24/49 ,  H01L25/071 ,  H01L29/1608 ,  H01L2224/33 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A power electronics module (10) comprises a first liquid cooler (12a) comprising a cooling channel (22) for receiving a cooling liquid, wherein the first liquid cooler (12a) comprises a metal body (20) providing a first terminal (24) of the power electronics module (10); a second liquid cooler (12b) comprising a cooling channel (22) for receiving a cooling liquid, wherein the second liquid cooler (12b) comprises a metal body (20) providing a second terminal (24) of the power electronics module (10); a plurality of semiconductor chips (14) arranged between the first liquid cooler (12a) and the second liquid cooler (12b), such that a first electrode (32a) of each semiconductor chip (14) is bonded to the first liquid cooler (12a), such that the first electrode (32a) is in electrical contact with the first liquid cooler (12a), and an opposite second electrode (32b) of each semiconductor chip (14) is in electrical contact with the second liquid cooler (12b); and an insulating encapsulation (18), formed by molding the first liquid cooler (12a), the second liquid cooler (12b) and the plurality of semiconductor chips (14) into an insulation material (16), such that the first liquid cooler (12a), the second liquid cooler (12b) and the plurality of semiconductor chips (14) are at least partially embedded onto the insulation material (16).

Abstract translation: 电力电子模块（10）包括第一液体冷却器（12a），其包括用于接收冷却液体的冷却通道（22），其中所述第一液体冷却器（12a）包括提供第一端子（24）的金属体（20） 的功率电子模块（10）; 第二液体冷却器（12b），包括用于接收冷却液体的冷却通道（22），其中所述第二液体冷却器（12b）包括提供所述电力电子模块（10）的第二端子（24）的金属体（20） ; 布置在第一液体冷却器（12a）和第二液体冷却器（12b）之间的多个半导体芯片（14），使得每个半导体芯片（14）的第一电极（32a）接合到第一液体冷却器（12a） ），使得第一电极（32a）与第一液体冷却器（12a）电接触，并且每个半导体芯片（14）的相对的第二电极（32b）与第二液体冷却器（12a）电接触， ; 以及通过将第一液体冷却器（12a），第二液体冷却器（12b）和多个半导体芯片（14）模制成绝缘材料（16）而形成的绝缘封装（18），使得第一液体冷却器 12a），第二液体冷却器（12b）和多个半导体芯片（14）至少部分地嵌入绝缘材料（16）上。

公开(公告)号：WO2015086184A1

公开(公告)日：2015-06-18

申请号：PCT/EP2014/070729

申请日：2014-09-29

Applicant: ABB TECHNOLOGY AG

Inventor： SCHUDERER, Jürgen ,  COTTET, Didier ,  HABERT, Mathieu ,  KICIN, Slavo ,  KEARNEY, Daniel ,  CANALES, Francisco

IPC: H01L25/07 ,  H01L23/46 ,  H01L23/473

CPC classification number: H01L25/074 ,  H01L23/3735 ,  H01L23/427 ,  H01L23/473 ,  H01L23/49811 ,  H01L24/36 ,  H01L24/40 ,  H01L24/41 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/37099

Abstract: A semiconductor stack arrangement (100, 100') and a power semiconductor module with such stack arrangement (100, 100') is proposed. The stack arrangement (100, 100') comprises a first semiconductor chip (102) with a planar terminal (106) mounted to a side (108) of the first semiconductor chip (102) and a second semiconductor chip (104) with a planar terminal (116) mounted to a side (118) of the second semiconductor chip (104). The stack arrangement (100, 100') further comprises an interposer (128, 128') arranged between the first semiconductor chip (102) and the second semiconductor chip (104), which interposer (128, 128) is adapted for electrically connecting the planar terminal (106) of the first semiconductor chip (102) and the planar terminal (116) of the second semiconductor chip (104). A first side (130) of the interposer (128, 128') is in thermal contact with the planar terminal (106) of the first semiconductor chip (102) and a second side (132) of the interposer (128, 128') is in thermal contact with the planar terminal (116) of the second semiconductor chip (104), and the interposer (128, 128') comprises a at least one channel or a plurality of channels (134) adapted for cooling the first semiconductor chip (102) and the second semiconductor chip (104). The interposer is manufactured from an electrically and thermally conductive material and/or alloy.

Abstract translation: 提出了一种具有这种堆叠装置（100,100'）的半导体堆叠装置（100,100'）和功率半导体模块。 堆叠装置（100,100'）包括第一半导体芯片（102），其具有安装到第一半导体芯片（102）的侧面（108）的平面端子（106）和具有平面的第二半导体芯片（104） 端子（116）安装到第二半导体芯片（104）的侧面（118）。 堆叠装置（100,100'）还包括布置在第一半导体芯片（102）和第二半导体芯片（104）之间的插入器（128,128'），该插入器（128,128）适于电连接 第一半导体芯片（102）的平面端子（106）和第二半导体芯片（104）的平面端子（116）。 插入器（128,128'）的第一侧（130）与第一半导体芯片（102）的平面端子（106）和插入件（128,128'）的第二侧（132）热接触， 与第二半导体芯片（104）的平面端子（116）热接触，并且插入器（128,128'）包括适于冷却第一半导体芯片的至少一个通道或多个通道（134） （102）和第二半导体芯片（104）。 插入器由导电和导热材料和/或合金制成。

公开(公告)号：WO2015121015A1

公开(公告)日：2015-08-20

申请号：PCT/EP2015/050611

申请日：2015-01-14

Applicant: ABB TECHNOLOGY AG

Inventor： HARTMANN, Samuel ,  COTTET, Didier ,  KICIN, Slavo

IPC: H01L23/64 ,  H01L25/07 ,  H03K17/082 ,  H03K17/12

CPC classification number: H01L29/7393 ,  H01L23/02 ,  H01L23/645 ,  H01L24/48 ,  H01L25/072 ,  H01L27/088 ,  H01L29/41708 ,  H01L29/4232 ,  H01L2224/4813 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/13055 ,  H02M1/088 ,  H03K17/0424 ,  H03K17/08116 ,  H03K17/0828 ,  H03K17/127 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor module (10) comprises at least one semiconductor chip (12) comprising at least one semiconductor switch (14) having a collector (18), emitter (22) and gate (20), a collector terminal (24) connected to the collector (18), gate terminal (26) connected to the gate (20), an emitter terminal (28) connected to the emitter (22) via an emitter conductor path (30) having an emitter inductance (32), an auxiliary emitter terminal (38) connected to the emitter (22), a first conductor path (34) connected to the emitter (22), and a second conductor path (36) connected to the emitter (22) having a different mutually inductive coupling with the emitter conductor path (30) as the first conductor path (34). The first conductor path (34) and the second conductor path (36) are connectable to the auxiliary emitter terminal (38) and/or the first conductor path (34) is connected to the auxiliary emitter terminal (38) and the second conductor path (36) is connected to a second auxiliary emitter terminal (44). The semiconductor switch (14) is an IGBT and each of the first conductor path (34) and the second conductor path (36) comprises bridging points (40) for connecting the respective conductor path to the auxiliary emitter terminal (38).

Abstract translation: 半导体模块（10）包括至少一个半导体芯片（12），其包括至少一个具有集电极（18），发射极（22）和栅极（20）的半导体开关（14），集电极端子（24） 集电极（18），连接到栅极（20）的栅极端子（26），经由具有发射极电感（32）的发射极导体路径（30）连接到发射极（22）的发射极端子（28） 连接到发射器（22）的端子（38），连接到发射器（22）的第一导体路径（34）和连接到发射器（22）的第二导体路径（36），其具有与 发射极导体路径（30）作为第一导体路径（34）。 第一导体路径（34）和第二导体路径（36）可连接到辅助发射极端子（38）和/或第一导体路径（34）连接到辅助发射极端子（38）和第二导体路径 （36）连接到第二辅助发射极端子（44）。 半导体开关（14）是IGBT，并且第一导体路径（34）和第二导体路径（36）中的每一个包括用于将各个导体路径连接到辅助发射极端子（38）的桥接点（40）。