公开(公告)号：WO1997045998A2

公开(公告)日：1997-12-04

申请号：PCT/US1997009141

申请日：1997-05-30

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  MURRAY, Brian, P. ,  CURRAN, Philip, A. ,  PRENDERGAST, Colm, J. ,  CUMMINS, Timothy, J.

IPC: H04N00/00

CPC classification number: H03H17/06 ,  H04N7/0102 ,  H04N9/64

Abstract: A novel finite impulse response filter apparatus and method are disclosed. A multiplexed data stream composed of two or more data streams is provided as an input to a tapped delay line. Weight and sum operators are connected to the even or odd delay line taps and generate a filtered output. The filter operates on one data stream per cycle and generates a multiplexed output. In another form, odd weight and sum operators are connected to and odd taps and even weight and sum operators are connected to the odd taps generating two filtered outputs. The filter operates on both data streams in each cycle and generates two multiplexed outputs. A crossbar switch is disclosed for parsing the multiplexed outputs into the constituent filtered data streams. The filter stages may be cascaded.

Abstract translation: 公开了一种新颖的有限脉冲响应滤波器装置和方法。 提供由两个或多个数据流组成的复用数据流作为抽头延迟线的输入。 重量和和运算符连接到偶数或奇数延迟线抽头，并生成滤波输出。 滤波器对每个周期的一个数据流进行操作，并产生多路输出。 在另一种形式中，奇数和和运算符连接到奇数抽头，甚至重量和和运算符连接到产生两个滤波输出的奇数抽头。 滤波器在每个周期中对两个数据流进行操作，并生成两个多路复用输出。 公开了一种用于将多路复用输出解析为组成滤波数据流的交叉开关。 过滤器级可以级联。

公开(公告)号：WO1997029546A1

公开(公告)日：1997-08-14

申请号：PCT/US1997001674

申请日：1997-02-11

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  SHERRY, Adrian ,  MCCARTNEY, Damien

IPC: H03M01/06

CPC classification number: H03M1/1076 ,  H03M1/12

Abstract: An invalid reference detection circuit (10) is formed on a semiconductor chip having reference input terminals adapted for coupling to a reference source (12) external to the chip, a local reference source (14), and comparison circuit (15). The comparison circuit is responsive to the local reference source and a condition at the reference input terminals to detect an invalid condition at the reference input terminals and produce an output signal (17) indicative of the condition. The invalid condition at the reference input terminals may be an open circuit, a voltage across the reference input terminals being below a predetermined minimum or above a predetermined maximum, and/or short circuit. An analog/digital conversion system (8) is formed on a semiconductor chip together with the invalid reference detection circuit. The reference input terminals are adapted for coupling to the conversion circuitry.

Abstract translation: 在具有参考输入端子的半导体芯片上形成无效参考检测电路（10），该参考输入端子适于与芯片外部的参考源（12）耦合，本地参考源（14）和比较电路（15）。 比较电路响应于本地参考源和参考输入端子处的条件，以检测参考输入端子处的无效状态，并产生指示条件的输出信号（17）。 在参考输入端子处的无效状态可以是开路，参考输入端子两端的电压低于预定最小值或高于预定最大值，和/或短路。 模拟/数字转换系统（8）与无效参考检测电路一起形成在半导体芯片上。 参考输入端适于耦合到转换电路。

公开(公告)号：WO1997020396A2

公开(公告)日：1997-06-05

申请号：PCT/US1996018682

申请日：1996-11-20

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  RUSSELL, Mark, A. ,  RIBNER, David, B.

IPC: H04B00/00

CPC classification number: H04M11/062 ,  H04Q2213/13034 ,  H04Q2213/13174 ,  H04Q2213/1319 ,  H04Q2213/13199 ,  H04Q2213/13305 ,  H04Q2213/1332

Abstract: A data transmission system including a telephone service subscriber loop utilized for transmission of data including telephone service signals; a splitter operable for splitting the subscriber loop into a first transmission path including a low pass filter which accommodates a continuation of telephone service signal transmissions along the subscriber loop and a second transmission path, said second transmission path including a capacitive element for attenuating the telephone service signals; and a digital subscriber loop transceiver coupled to the second transmission path for implementing high rate digital data transmission over the subscriber loop, the transceiver including a frontend processing circuit having a transmit path and a receive path, at least said receive path comprising a high pass filter for further attenuating said telephone service signals. The capacitive element in the second transmission path and the high pass filter in the receive path of the transceiver frontend operate in conjunction to maintain transhybrid loss.

Abstract translation: 一种数据传输系统，包括用于传输包括电话业务信号的数据的电话业务用户环路; 分离器，其可操作用于将所述用户环路分解成包括低通滤波器的第一传输路径，所述低通滤波器容纳沿着所述用户环路和第二传输路径的电话服务信号传输的延续，所述第二传输路径包括用于衰减所述电话服务 信号; 耦合到第二传输路径的数字用户环路收发机，用于通过用户环路实现高速率数字数据传输，该收发器包括具有发射路径和接收路径的前端处理电路，至少所述接收路径包括高通滤波器 用于进一步衰减所述电话服务信号。 第二传输路径中的电容元件和收发器前端的接收路径中的高通滤波器一起工作，以保持变压器损耗。

公开(公告)号：WO1997012442A1

公开(公告)日：1997-04-03

申请号：PCT/US1996014429

申请日：1996-09-11

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  GOEL, Rakesh

IPC: H03K03/037

CPC classification number: H03K3/2893 ,  H03K17/063 ,  H03K17/6871

Abstract: A hysteresis circuit including first (88) and second (90) voltage reference circuits responsive to an input control signal ((VA) for providing first and second voltage levels connected in series to produce a higher voltage level; a first switching circuit (82), responsive to the voltage reference circuits to turn on and provide an output drive signal when the higher voltage is reached; a second switching circuit (84), responsive to the first switching circuit turning on, for removing one of the first and second voltage levels to produce a lower voltage level; the first switching circuit turning off in response to the input level control signal decreasing below the lower voltage level.

Abstract translation: 响应于用于提供串联连接以产生较高电压电平的第一和第二电压电平的输入控制信号（（VA）），包括第一（88）和第二（90）电压参考电路的滞后电路;第一开关电路（82） 响应于所述电压参考电路导通并在达到较高电压时提供输出驱动信号;第二开关电路（84），响应于所述第一开关电路导通，用于去除所述第一和第二电压电平之一 以产生较低的电压电平;第一开关电路响应于输入电平控制信号降低到较低电压电平以下而关断。

公开(公告)号：WO1997012402A1

公开(公告)日：1997-04-03

申请号：PCT/US1996015285

申请日：1996-09-24

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  MUNROE, Scott, C.

IPC: H01L29/768

CPC classification number: H01L29/76816 ,  H01L29/42396 ,  H01L29/768 ,  H01L29/772 ,  H01L29/7831 ,  H01L29/94

Abstract: A semiconductor device having a semiconductor region including a material of a first predetermined conductivity type; an insulating layer (40) provided on the semiconductor region; a gate electrode (32, 34, 38) provided on the insulating layer, the gate electrode forming a potential well within the semiconductor region in response to a potential being applied thereto; and a diffusion (36) of highly doped material of a second predetermined conductivity type being positioned within the semiconductor region, and which is applied through an opening in the gate electrode and the insulating layer (40), the diffusion (36) being in direct ohmic contact with the potential well. The diffusion (36) can be either a n+ or p+ diffusion. The diffusion (36) accommodates a reduction in lateral time constants of charge redistribution within the potential well, direct sensing of the charge in the well, and injection and extraction of charge to and from the well.

Abstract translation: 一种半导体器件，具有包括第一预定导电类型的材料的半导体区域; 设置在所述半导体区域上的绝缘层（40） 设置在所述绝缘层上的栅极电极，所述栅极电极响应于施加到所述栅电极的电位而在所述半导体区域内形成势阱; 并且第二预定导电类型的高掺杂材料的扩散（36）位于半导体区域内，并且通过栅电极和绝缘层（40）中的开口施加，扩散（36）直接 欧姆接触势阱。 扩散（36）可以是n +或p +扩散。 扩散（36）可以减少潜在井内的电荷再分配的横向时间常数，直接感测井中的电荷，以及向井和从井的注入和提取电荷。

公开(公告)号：WO1997009790A1

公开(公告)日：1997-03-13

申请号：PCT/US1996002743

申请日：1996-03-01

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  HITCHCOX, David ,  SHEPHERD, Paul

IPC: H03M13/00

CPC classification number: H03H21/0012 ,  G11B20/10009 ,  H03H17/0664 ,  H04L7/0062 ,  H04L7/10

Abstract: A decimating PRML signal processor system (10) for processing a PRML data signal includes: an adaptive filter circuit (22) for receiving and for shaping the data signal; a gain control circuit (30), responsive to the adaptive filter circuit (22), for adjusting the gain of the data signal; a phase control circuit (32), responsive to the adaptive filter circuit (22), for adjusting the phase of the data signal; a clock circuit (40) for providing signals for driving each of the circuits; and a decimation controller (42) for reducing the rate of the clock signals to at least one of the circuits to decrease the power required to operate the system.

Abstract translation: 用于处理PRML数据信号的抽取PRML信号处理器系统（10）包括：自适应滤波器电路（22），用于接收和整形数据信号; 响应于所述自适应滤波器电路（22）的增益控制电路（30），用于调整所述数据信号的增益; 响应于所述自适应滤波器电路（22）的相位控制电路（32），用于调整所述数据信号的相位; 时钟电路（40），用于提供用于驱动每个电路的信号; 以及抽取控制器（42），用于将时钟信号的速率降低到至少一个电路以降低操作系统所需的功率。

公开(公告)号：WO1996041413A1

公开(公告)日：1996-12-19

申请号：PCT/US1996009977

申请日：1996-06-06

Applicant: ANALOG DEVICES, INC. ,  GILBERT, Barrie

Inventor： ANALOG DEVICES, INC.

IPC: H03F03/45

CPC classification number: H03G7/06 ,  H03G7/001

Abstract: A gain control circuit (22) provides linear-in-decibel gain control for an RF signal variable gain amplifier (12). The gain control circuit (22) utilizes the transconductance characteristics of bipolar transistors to generate a logarithmic relationship betweena gain control current (IG) and an amplifier bias current (IC). The gain control circuit (22) comprises essentially a current mirror having two transistors (Q1, Q2) with a resistor (R1) coupled between the associated base terminals of the two transistors (Q1, Q2). A third transistor (Q3) and a resistor (R2) are also provided to absorb the gain control current (IG). The gain control current (IG) is applied to a base of a first one (Q1) of the two transistors and a voltage is thereby established across the resistor. This voltage subtracts from the base-emitter voltage of the second transistor (Q2) thereby producing a corresponding exponential reduction in the current through the second transistor (Q2). This current (IC) is provided to a gm stage (12), whose gain is linearly proportional to this current. Thus, a linear change in the gain control current (IG) produces an exponential change in the gainof the gm stage (12). Accordingly, a linear-in dB variable gain amplifier is achieved.

Abstract translation: 增益控制电路（22）为RF信号可变增益放大器（12）提供线性分贝增益控制。 增益控制电路（22）利用双极晶体管的跨导特性产生增益控制电流（IG）和放大器偏置电流（IC）之间的对数关系。 增益控制电路（22）基本上包括具有两个晶体管（Q1，Q2）的电流镜，电阻器（R1）耦合在两个晶体管（Q1，Q2）的相关联的基极之间。 还提供第三晶体管（Q3）和电阻器（R2）以吸收增益控制电流（IG）。 增益控制电流（IG）被施加到两个晶体管的第一个（Q1）的基极，并且由此在电阻器两端形成电压。 该电压从第二晶体管（Q2）的基极 - 发射极电压减去，从而产生通过第二晶体管（Q2）的电流的相应的指数减小。 该电流（IC）被提供给gm级（12），其增益与该电流成线性比例。 因此，增益控制电流（IG）的线性变化产生gm级（12）的增益的指数变化。 因此，实现了线性dB的可变增益放大器。

公开(公告)号：WO1996032650A1

公开(公告)日：1996-10-17

申请号：PCT/US1996004856

申请日：1996-04-09

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  KUNG, Joseph, T.

IPC: G01P15/08

CPC classification number: G01P15/0802 ,  B81C1/00611 ,  B81C2201/0119 ,  G01P1/023 ,  G01P2015/0828

Abstract: A method for fabricating a micromechanical device (48) and a semiconductor circuit (70) on a substrate (10) includes the steps of forming the micromechanical device (48) on a device area (58) of the substrate (10), the micromechanical device (48) being embedded in a sacrificial material (22, 34, 42), selectively depositing a planarization layer (54) on the substrate (10) in a circuit area (56) thereof, forming the semiconductor circuit (70) on the planarization layer (54) in the circuit area (56) and removing the sacrificial material (22, 34, 42) from the embedded micromechanical device (48). In a preferred embodiment, the planarization layer is an epitaxial silicon layer (54). A protective cap (98) may be formed over the micromechanical device (48), so that it is completely encapsulated and is thereby protected against particulate contamination.

Abstract translation: 在衬底（10）上制造微机械器件（48）和半导体电路（70）的方法包括以下步骤：在衬底（10）的器件区域（58）上形成微机械器件（48），所述微机械 器件（48）嵌入在牺牲材料（22,34,42）中，在其电路区域（56）中在衬底（10）上选择性地沉积平坦化层（54），在其上形成半导体电路（70） 平面化层（54），并且从嵌入式微机械装置（48）去除牺牲材料（22,34,42）。 在优选实施例中，平坦化层是外延硅层（54）。 可以在微机械装置（48）上方形成保护盖（98），使得其完全被包封，从而防止颗粒污染。

公开(公告)号：WO1996017256A1

公开(公告)日：1996-06-06

申请号：PCT/US1995015286

申请日：1995-11-29

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  CHAU, Kevin, Hin-Leung ,  HOWE, Roger, T. ,  PAYNE, Richard, S. ,  ZHAO, Yang ,  CORE, Theresa ,  SHERMAN, Steven, J.

IPC: G01P15/125

CPC classification number: G01P15/125 ,  G01P15/0802 ,  G01P2015/0814

Abstract: A method and apparatus for providing a conductive plane (40) beneath a suspended microstructure. A conductive region is diffused into a substrate. A dielectric layer is added, covering the substrate, and then removed from a portion of the conductive region. A spacer layer is deposited over the dielectric and exposed conductive region. A polysilicon layer is deposited over the spacer layer, and formed into the shape of the suspended microstructure. After removal of the spacer layer, the suspended microstructure is left free to move above an exposed conductive plane (40). The conductive plane is driven to the same potential as the microstructure.

Abstract translation: 一种用于在悬浮微结构下方提供导电平面（40）的方法和装置。 导电区域扩散到基板中。 添加介电层，覆盖基板，然后从导电区域的一部分去除。 间隔层沉积在电介质和暴露的导电区域上。 在间隔层上沉积多晶硅层，并形成为悬浮微结构的形状。 在去除间隔层之后，悬浮的微结构保持自由以在暴露的导电平面（40）上移动。 导电平面被驱动到与微结构相同的电位。

公开(公告)号：WO1996017254A1

公开(公告)日：1996-06-06

申请号：PCT/US1995015468

申请日：1995-11-29

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  TSANG, Robert, W., K. ,  FARASH, Jeffrey, A. ,  PAYNE, Richard, S.

IPC: G01P15/08

CPC classification number: B81C1/0015 ,  B81C2201/0136 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814

Abstract: A method for providing a conductive ground plane beneath a suspended microstructure. A conductive region is diffused into a substrate. Two dielectric layers are added: first a thermal silicon dioxide layer and then a silicon nitride layer. A first mask is used to etch a ring partially through the silicon nitride layer. Then, a second mask is used to etch a hole through both dielectric layers in a region having a perimeter that extends between the inner and outer edges of the ring. This leaves the conductive region exposed in an area surrounded by a ring that has the silicon dioxide layer and a narrow silicon nitride layer. The ring is surrounded by an area in which the silicon dioxide and silicon nitride layers have not been reduced. A spacer silicon dioxide layer is deposited over the dielectric and then a polysilicon layer is deposited and formed into the shape of a suspended microstructure. When the spacer layer is etched away, the silicon dioxide under the narrow silicon nitride layer is removed, along with the narrow silicon nitride layer, leaving an exposed ground plane surrounded by a dielectric with minimal undercutting.

Abstract translation: 一种用于在悬浮微结构下面提供导电接地平面的方法。 导电区域扩散到衬底中。 加入两个电介质层：首先是热二氧化硅层，然后是氮化硅层。 使用第一掩模来部分地蚀刻环通过氮化硅层。 然后，使用第二掩模在具有在环的内边缘和外边缘之间延伸的周边的区域中的两个电介质层上蚀刻孔。 这使得导电区域暴露在由具有二氧化硅层和窄氮化硅层的环包围的区域中。 环被二氧化硅和氮化硅层未被还原的区域包围。 在电介质上沉积间隔二氧化硅层，然后沉积多晶硅层并形成悬浮微结构的形状。 当蚀刻间隔层时，与窄氮化硅层一起除去窄氮化硅层下面的二氧化硅，留下暴露的接地平面，其中包含极少的底切。