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    Sealed MEMS devices with multiple chamber pressures
    1.
    发明授权
    Sealed MEMS devices with multiple chamber pressures 有权
    密封的MEMS器件具有多个腔室压力

    公开(公告)号：US09102512B2

    公开(公告)日：2015-08-11

    申请号：US14045855

    申请日：2013-10-04

    Applicant: Analog Devices, Inc.

    Inventor： Christine H. Tsau ,  Li Chen ,  Kuang L. Yang

    IPC: H01L29/84 ,  B81B7/00 ,  B81C1/00

    CPC classification number: B81B7/0038 ,  B81B2201/0235 ,  B81B2201/0242 ,  G01P1/023 ,  G01P15/0802 ,  H01L29/84

    Abstract: A MEMS apparatus has a substrate, a cap forming first and second chambers with the base, and movable microstructure within the first and second chambers. To control pressures, the MEMS apparatus also has a first outgas structure within the first chamber. The first outgas structure produces a first pressure within the first chamber, which is isolated from the second chamber, which, like the first chamber, has a second pressure. The first pressure is different from that in the second pressure (e.g., a higher pressure or lower pressure).

    Abstract translation: MEMS装置具有基板，形成具有基座的第一和第二室的盖以及第一和第二室内的可移动微结构。 为了控制压力，MEMS装置还在第一室内具有第一排气结构。 第一排气结构在第一室内产生第一压力，该第一压力与第二室隔离，其与第一室相似，具有第二压力。 第一压力与第二压力（例如，较高压力或更低压力）不同。

    Microchip with blocking apparatus and method of fabricating microchip
    3.
    发明授权
    Microchip with blocking apparatus and method of fabricating microchip 有权
    Microchip具有制造微芯片的阻塞装置和方法

    公开(公告)号：US08749036B2

    公开(公告)日：2014-06-10

    申请号：US13673124

    申请日：2012-11-09

    Applicant: Analog Devices, Inc.

    Inventor： Li Chen ,  Thomas Kieran Nunan ,  Kuang L. Yang

    IPC: H01L23/06 ,  H01L23/02 ,  H01L23/34

    CPC classification number: B81C3/001 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/0109 ,  B81C2203/019 ,  B81C2203/035

    Abstract: A microchip has a base die with a conductive interconnect and an isolation trench around at least a portion of the conductive interconnect, and a cap die secured to the base die. A seal, formed from a metal material, is positioned between the base die and the cap die to secure them together. The microchip also has a blocking apparatus, between the isolation trench and the metal seal, that at least in part prevents the metal material from contacting the interconnect.

    Abstract translation: 微芯片具有基底裸片，其具有导电互连和围绕导电互连的至少一部分的隔离沟槽，以及固定到基模的帽模。 由金属材料形成的密封件位于基模和盖模之间，以将它们固定在一起。 微芯片还具有在隔离沟槽和金属密封件之间的阻挡装置，至少部分地防止金属材料与互连件接触。

    MICROELECTROMECHANICAL SYSTEMS (MEMS) AND RELATED PACKAGES
    4.
    发明申请
    MICROELECTROMECHANICAL SYSTEMS (MEMS) AND RELATED PACKAGES 有权

    公开(公告)号：US20250118715A1

    公开(公告)日：2025-04-10

    申请号：US18730912

    申请日：2023-01-24

    Applicant: Analog Devices, Inc.

    Inventor： Xin Zhang ,  Jianglong Zhang ,  Li Chen ,  John C. Cowles ,  Michael Judy ,  Shafi Saiyed

    IPC: H01L25/16 ,  B81B7/00 ,  H01L23/538

    Abstract: Compact packages including microelectromechanical system (MEMS) devices and multiple application specific integrated circuits (ASICs) are described. These packages are sufficiently small to be applicable to contexts in which space requirements are particularly strict, such as in consumer electronics. These packages involve vertical die stacks. A first ASIC may be positioned on one side of the die stack and another ASIC may be positioned on the other side of the die stack. A die including a MEMS device (e.g., an accelerometer, gyroscope, switch, resonator, optical device) is positioned between the ASICs. Optionally, an interposer serving as cap substrate for the MEMS device is also positioned between the ASICs. In one example, a package of the types described herein has an extension of 2 mm×2 mm in the planar axes and less than 500-800 μm in height.

    Microchip with blocking apparatus
    6.
    发明授权
    Microchip with blocking apparatus 有权
    Microchip具有阻塞装置

    公开(公告)号：US09242856B2

    公开(公告)日：2016-01-26

    申请号：US14224107

    申请日：2014-03-25

    Applicant: Analog Devices, Inc.

    Inventor： Li Chen ,  Thomas Kieran Nunan ,  Kuang L. Yang

    IPC: H01L23/06 ,  H01L23/34 ,  H01L23/12 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  B81C3/00 ,  B81C1/00

    CPC classification number: B81C3/001 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/0109 ,  B81C2203/019 ,  B81C2203/035

    Abstract: A microchip has a base die with a conductive interconnect and an isolation trench around at least a portion of the conductive interconnect, and a cap die secured to the base die. A seal, formed from a metal material, is positioned between the base die and the cap die to secure them together. The microchip also has a blocking apparatus, between the isolation trench and the metal seal, that at least in part prevents the metal material from contacting the interconnect.

    Abstract translation: 微芯片具有基底裸片，其具有导电互连和围绕导电互连的至少一部分的隔离沟槽，以及固定到基模的帽模。 由金属材料形成的密封件位于基模和盖模之间，以将它们固定在一起。 微芯片还具有在隔离沟槽和金属密封件之间的阻挡装置，至少部分地防止金属材料与互连件接触。

    Microchip with Blocking Apparatus and Method of Fabricating Microchip
    7.
    发明申请
    Microchip with Blocking Apparatus and Method of Fabricating Microchip 有权
    Microchip具有封装装置和制造Microchip的方法

    公开(公告)号：US20140203422A1

    公开(公告)日：2014-07-24

    申请号：US14224107

    申请日：2014-03-25

    Applicant: Analog Devices, Inc.

    Inventor： Li Chen ,  Thomas Kieran Nunan ,  Kuang L. Yang

    IPC: B81B7/00

    CPC classification number: B81C3/001 ,  B81B7/007 ,  B81C1/00269 ,  B81C2203/0109 ,  B81C2203/019 ,  B81C2203/035

    Abstract: A microchip has a base die with a conductive interconnect and an isolation trench around at least a portion of the conductive interconnect, and a cap die secured to the base die. A seal, formed from a metal material, is positioned between the base die and the cap die to secure them together. The microchip also has a blocking apparatus, between the isolation trench and the metal seal, that at least in part prevents the metal material from contacting the interconnect.

    Abstract translation: 微芯片具有基底裸片，其具有导电互连和围绕导电互连的至少一部分的隔离沟槽，以及固定到基模的帽模。 由金属材料形成的密封件位于基模和盖模之间，以将它们固定在一起。 微芯片还具有在隔离沟槽和金属密封件之间的阻挡装置，至少部分地防止金属材料与互连件接触。

    SELF-CALIBRATED HEAVY METAL DETECTOR
    8.
    发明申请
    SELF-CALIBRATED HEAVY METAL DETECTOR 审中-公开

    公开(公告)号：US20180172631A1

    公开(公告)日：2018-06-21

    申请号：US15383415

    申请日：2016-12-19

    Applicant: Analog Devices, Inc.

    Inventor： Chen Yang ,  Yumeng Liu ,  Li Chen ,  Kuang L. Yang

    IPC: G01N27/447

    Abstract: A microfluidic ion detector for detecting heavy metal ions in liquid and particulate matter from gas samples is described. The microfluidic ion detector includes a sample extraction structure for extracting sample ions from a sample liquid or extracting sample ions from the particulate matter of a gas sample, a separation structure for separating sample ions of different types once extracted, and a detection structure for detecting the sample ions. The microfluidic ion detector also includes a reference reservoir providing a reference ion against which the sample may be calibrated based on the operation of the separation structure. A portable, self-calibrating ion detector may be realized by including the described components on a single substrate.

    Method of etching a wafer
    9.
    发明授权
    Method of etching a wafer 有权
    蚀刻晶片的方法

    公开(公告)号：US09150408B2

    公开(公告)日：2015-10-06

    申请号：US14338754

    申请日：2014-07-23

    Applicant: Analog Devices, Inc.

    Inventor： Li Chen ,  Mitul Dalal

    IPC: H01L23/02 ,  B81C1/00 ,  H01L21/48 ,  H01L21/50 ,  H01L23/04 ,  B81B7/00

    CPC classification number: B81C1/00269 ,  B81B7/0058 ,  B81C1/00333 ,  B81C1/00523 ,  B81C2203/0118 ,  H01L21/4803 ,  H01L21/50 ,  H01L23/04 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of etching a plurality of cavities in a wafer provides a wafer having a patterned hard mask layer. The patterned hard mask has open areas defining locations for first cavities and second cavities. A mask is applied to cover the patterned hard mask layer. The mask is etched to remove wafer material from areas defined by the second cavities. The mask is removed and etching then removes wafer material except as prevented by the hard mask layer. This leaves the first cavities with a first depth and further deepens the second cavities to a depth greater than the first depth. By suitably configuring the second cavities, a capped die can be formed by securing the wafer to a second wafer and removing at least a portion of the unsecured side of the first wafer to expose the second cavities, thereby forming a plurality of caps on the second wafer.

    Abstract translation: 蚀刻晶片中的多个空腔的方法提供具有图案化硬掩模层的晶片。 图案化的硬掩模具有限定第一腔和第二腔的位置的开放区域。 施加掩模以覆盖图案化的硬掩模层。 蚀刻掩模以从由第二腔限定的区域中去除晶片材料。 除去掩模，然后蚀刻除去硬掩模层所防止的晶片材料。 这使得第一空腔具有第一深度并且进一步将第二空腔加深至大于第一深度的深度。 通过适当地构造第二空腔，可以通过将晶片固定到第二晶片并且移除第一晶片的不安全侧的至少一部分以暴露第二空腔来形成封盖的裸片，由此在第二晶圆上形成多个盖 晶圆。

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