公开(公告)号：DE3584859D1

公开(公告)日：1992-01-23

申请号：DE3584859

申请日：1985-05-24

Applicant: IBM

Inventor： RYAN PHILIP MEADE ,  AICHELMANN JR

IPC: G06F12/16 ,  G06F11/07 ,  G06F11/10 ,  G06F11/00

公开(公告)号：DE3584318D1

公开(公告)日：1991-11-14

申请号：DE3584318

申请日：1985-05-21

Applicant: IBM

Inventor： AICHELMANN JR ,  BLUMBERG REX HAROLD ,  MELTZER DAVID ,  POMERENE JAMES HERBERT ,  PUZAK THOMAS ROBERTS ,  RECHTSCHAFFEN RUDOLPH NATHAN ,  SPARACIO FRANK JOHN

IPC: G06F12/08 ,  G06F12/0897

公开(公告)号：DE3586851D1

公开(公告)日：1993-01-07

申请号：DE3586851

申请日：1985-06-03

Applicant: IBM

Inventor： AICHELMANN JR ,  LANGE LAWRENCE KENNETH

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/00

Abstract: An error correction code, especially suited for memory chips with multi-bit outputs, in which parity bits are calculated for each byte of the word and check bits are calculated for the word as a whole. In a 4-byte, 32-bit word, eight bits of error correction can correct up to four errors if the errors are restricted to corresponding bits in the 4 bytes.

公开(公告)号：DE2962948D1

公开(公告)日：1982-07-15

申请号：DE2962948

申请日：1979-06-01

Applicant: IBM

Inventor： AICHELMANN JR

IPC: G11C11/56 ,  G11C19/28 ,  G11C27/04 ,  H01L21/339 ,  H01L29/762 ,  G11C27/02

公开(公告)号：DE3586851T2

公开(公告)日：1993-06-09

申请号：DE3586851

申请日：1985-06-03

Applicant: IBM

Inventor： AICHELMANN JR ,  LANGE LAWRENCE KENNETH

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/00

Abstract: An error correction code, especially suited for memory chips with multi-bit outputs, in which parity bits are calculated for each byte of the word and check bits are calculated for the word as a whole. In a 4-byte, 32-bit word, eight bits of error correction can correct up to four errors if the errors are restricted to corresponding bits in the 4 bytes.

公开(公告)号：DE3177245D1

公开(公告)日：1991-07-11

申请号：DE3177245

申请日：1981-08-10

Applicant: IBM

Inventor： AICHELMANN JR ,  NEVES FERNANDO

IPC: G11C19/00 ,  G11C19/28 ,  G11C27/04

Abstract: A recirculating loop memory array is adapted for the parallel as well as serial fetching and storing of data while requiring only a single input and single output data terminal. Each (1, 2...N) of the array is provided with a shift register stage (1', 2'...N') for parallel data accessing. A particular recirculating bit in all of the loops can be fetched in parallel into their respective shift register stages and, conversely, the bits stored in the shift register stages can be loaded in parallel into predetermined recirculating bits of their respective loops. The shift register (7) is operated at high speed so that it may be completely loaded or unloaded during the interval between successive steppings of the loops.

公开(公告)号：DE3380910D1

公开(公告)日：1990-01-04

申请号：DE3380910

申请日：1983-05-27

Applicant: IBM

Inventor： AICHELMANN JR ,  LANGE LAWRENCE K

IPC: G06F11/10 ,  G06F12/16 ,  G11C29/00 ,  G06F11/00