公开(公告)号：US3699530A

公开(公告)日：1972-10-17

申请号：US3699530D

申请日：1970-12-30

Applicant: IBM

Inventor： CAPOWSKI ROBERT S ,  UNTERBERGER ROBERT M ,  HORSMAN LARRY R

IPC: G06F13/12 ,  G06F13/18 ,  G06F9/18

CPC classification number: G06F13/18 ,  G06F13/122

Abstract: A storage control unit (SCU) for a data processing system which buffers data fetch and data store requests from input/output channels for access to low-speed high-capacity interleaved logical storage units. Multiple dedicated buffers are provided for each channel in the storage control unit (SCU) to insure that all channels have an individual receptacle to transfer data to which cannot be made unavailable due to transfers by other channels. Priority resolution of requests from channels controls the use of the in bus from the channel to the SCU independently of subsequent priority resolution for use of the main storage. Once a channel transfers its storage address and data into its assigned SCU buffer, that buffer, based on the storage address contained within it, enters storage priority for the particular logical storage unit desired. In this manner, the single queue of channel requests is rearranged into four independent request queues based on logical storage addresses.

Abstract translation: 一种用于数据处理系统的存储控制单元（SCU），用于缓冲来自输入/输出通道的数据提取和数据存储请求，用于访问低速大容量交错逻辑存储单元。 为存储控制单元（SCU）中的每个通道提供多个专用缓冲器，以确保所有通道具有单独的插座以传输由于其他通道的传输而不能使其不可用的数据。 来自频道的请求的优先级分辨率控制从通道到SCU的总线的使用，独立于随后使用主存储的优先级分辨率。 一旦通道将其存储地址和数据传输到其分配的SCU缓冲器中，则该缓冲器基于其中包含的存储地址，为所需的特定逻辑存储单元输入存储优先级。 以这种方式，基于逻辑存储地址将信道请求的单个队列重新排列成四个独立的请求队列。

公开(公告)号：US3626376A

公开(公告)日：1971-12-07

申请号：US3626376D

申请日：1970-05-14

Applicant: IBM

Inventor： ANDERSON LAWRENCE B ,  CAPOWSKI ROBERT S ,  HIATT GREGG C ,  MILLER JOSEPH H

IPC: G06F12/04 ,  G06F13/00

CPC classification number: G06F12/04

Abstract: A circuit is provided for transferring a multibyte word of data from a buffer memory to a main memory beginning at any available byte position in the main memory. A gating circuit is controlled in response to an address designating the starting byte position for skewing bytes from the buffer to the starting byte position and to any remaining byte positions of the first addressed word location of the memory. A set of registers and a gating circuit are provided for storing any remaining data bytes from the word read from the buffer. On subsequent transfers, data is transferred simultaneously from the buffer and the register to form a complete word for storage in the main memory and remaining bytes from the buffer are then entered into the register for a subsequent transfer.

公开(公告)号：FR2397015A1

公开(公告)日：1979-02-02

申请号：FR7818485

申请日：1978-06-13

Applicant: IBM

Inventor： CAPOWSKI ROBERT S ,  KRYGOWSKI MATTHEW A ,  ZIMMERMAN TERRENCE K

IPC: G06F13/28 ,  G06F12/04 ,  G06F13/12 ,  G06F13/18 ,  G06F3/04 ,  G06F13/00

Abstract: Storage access requests are forwarded from plural input/output channels to shared main storage. An address word in each request designates the identity of the source channel (CHID) and "destination" address (of a doubleword space in storage relative to which one, two or four "data" words shall be transferred). EOT tag signal provides demarcation of requests and also uniquely identifies "1-wide" input (Store) requests. Quadword (QW) tag, presented with "4-wide" requests, enables the storage access system to use a single address in the request to locate two contiguous doubleword spaces in storage. Data tags (D1, D2), presented on a selective basis enable the access system to selectively steer (reorder the positions of) data words in an input request relative to word halves of the addressed space. Consequently the data repositioning function associated with Read Backward operations does not require reordering of data words in the channel buffers (saving handling time and expense of "steering" circuits in the individual channels). In association with a "1-wide" input request a single data tag, D1 or D2, is used to steer the single data word of the request into either half of the addressed space on a selective basis.

公开(公告)号：CA2082078A1

公开(公告)日：1993-08-21

申请号：CA2082078

申请日：1992-11-04

Applicant: IBM

Inventor： BARTOW NEIL G ,  CAPOWSKI ROBERT S ,  FASANO LOUIS T ,  GREGG THOMAS A ,  SALYER GREGORY ,  WESTCOTT DOUGLAS W

IPC: G06F13/00 ,  G06F15/17 ,  H04L69/14 ,  H04L69/40

Abstract: A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements A, B of a data processing system are connected by a physical link comprising multiple conductors 100, 101 attached to transceivers 130, 140 at channels in each data processing element. Once the transceivers have been synchronized, commands and responses are exchanged which ensure that all of the transceivers in a channel are connected to the same channel on the other end of the conductor. If the transceivers are considered configured and an entry is made in a Configured-Transceiver table. A search is made of an Allowed-Operational-Link table which contains sets of transceivers which are allowed to become operational links. The set of transceivers thus found, is compared against the Configured-Transceiver-Table to verify that all of the members of the set have been configured. If a match is found, this set of transceivers becomes an Intended-Operational-Link. The Intended-Operational-Link is verified to ensure that both channels agree on the set of conductors will form the operational link. If the Intended-Operational-Link verifies, the operational link is established therefrom.

公开(公告)号：CA2082077A1

公开(公告)日：1993-08-21

申请号：CA2082077

申请日：1992-11-04

Applicant: IBM

Inventor： BARTOW NEIL G ,  BROWN PAUL J ,  CAPOWSKI ROBERT S ,  FASANO LOUIS T ,  GREGG THOMAS A ,  SALYER GREGORY ,  SUGRUE PATRICK J ,  WESTCOTT DOUGLAS W ,  ZEYAK VINCENT P JR

IPC: H04J3/06 ,  H04L25/02 ,  H04L69/40

Abstract: A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups do not have sequence numbers, therefore, the receiver determines which frames are part of a frame group by the arrival times of the individual frames. In one embodiment, the transceivers for each member of the parallel bus asynchronously achieve synchronism at each end of the fiber. Thus the need for a common clock is eliminated. The receivers on each side of the bus determine the relative skew for each conductor by performing skew measurements on a calibration message generated by the transmitters on the other side of the bus. When the skew on all conductors, viewed from both sides of the bus, has been determined, the skew values are exchanged across the bus, thus enabling the transmitters to set proper frame spacing.

公开(公告)号：CA986230A

公开(公告)日：1976-03-23

申请号：CA180753

申请日：1973-09-11

Applicant: IBM

Inventor： AHEARN THOMAS P ,  CHRISTENSEN NEAL T ,  GANNON PATRICK M ,  LEE ARLIN E ,  LIPTAY JOHN S ,  CAPOWSKI ROBERT S

IPC: G06F12/10

Abstract: This specification describes a virtual memory system in which a set of conversion tables is used to translate an arbitrarily assigned programming designation called a virtual address into an actual main memory location called a real address. To avoid the necessity of translating the same addresses over and over again, a table called the Directory Look Aside Table (DLAT) retains current virtual to real address translations for use where particular virtual addresses are requested more than once. Each translation retained by the DLAT is identified by an identifier (ID) that signifies the set of tables used in that translation. This identifier is compared with an identifier generated for the currently requested virtual address. If these identifiers match and the virtual address retained in the DLAT matches the currently requested virtual address, the translation stored in the DLAT may be used. If the identifiers or virtual address don't match, a new translation must be performed using the set of conversion tables associated with the currently requested address.

公开(公告)号：BR9300358A

公开(公告)日：1993-08-24

申请号：BR9300358

申请日：1993-01-28

Applicant: IBM

Inventor： BARTOW NEIL B ,  BROWN PAUL J ,  CAPOWSKI ROBERT S ,  FASANO LOUIS T ,  GREGG THOMAS A ,  SALYER GREGORY ,  SUGRUE PATRICK J ,  WESTCOTT DOUGLAS W ,  ZEYAK VINCENT P JR

IPC: H04J3/06 ,  H04L25/02 ,  H04L69/40 ,  H04B10/12

Abstract: A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups do not have sequence numbers, therefore, the receiver determines which frames are part of a frame group by the arrival times of the individual frames. In one embodiment, the transceivers for each member of the parallel bus asynchronously achieve synchronism at each end of the fiber. Thus the need for a common clock is eliminated. The receivers on each side of the bus determine the relative skew for each conductor by performing skew measurements on a calibration message generated by the transmitters on the other side of the bus. When the skew on all conductors, viewed from both sides of the bus, has been determined, the skew values are exchanged across the bus, thus enabling the transmitters to set proper frame spacing.

公开(公告)号：CA2089771A1

公开(公告)日：1993-08-21

申请号：CA2089771

申请日：1993-02-18

Applicant: IBM

Inventor： BARTOW NEIL G ,  BROWN PAUL J ,  CAPOWSKI ROBERT S ,  FASANO LOUIS T ,  GREGG THOMAS A ,  SALYER GREGORY ,  WESTCOTT DOUGLAS W

IPC: G06F13/00 ,  G06F13/12 ,  G06F13/38 ,  H04L69/40

Abstract: Buffers 54,58 are provided in two elements 52,56 between which data is to be transferred wherein both buffers are managed solely by the originator of the data transfer. Only one transfer is required to transmit a message, and a second transfer acknowledges the completion of the function because message delivery to the receiver is guaranteed under the implemented protocol. When a request is sent, a message timer is started at the sender. When the normal response for the request is received, the timer is reset; however, if the duration of the message operation exceeds the timeout value, a message-timeout procedure is initiated. When the cancel command is issued, a second timer is set. If this timer is exceeded, subsequent cancel commands can be issued. If subsequent cancel commands are issued, a cancel complete command must be sent and responded to. Since the commands must be executed in the sequence in which they are received, a response to the cancel complete command ensures that there are no other cancel operation commands remaining in the receiver, allowing subsequent operations to start without danger of being cancelled.

公开(公告)号：CA1103324A

公开(公告)日：1981-06-16

申请号：CA301828

申请日：1978-04-24

Applicant: IBM

Inventor： CAPOWSKI ROBERT S ,  KRYGOWSKI MATTHEW A ,  ZIMMERMAN TERRENCE K

IPC: G06F13/28 ,  G06F12/04 ,  G06F13/12 ,  G06F13/18 ,  G06F3/00

Abstract: REQUEST FORWARDING SYSTEM Storage access requests are forwarded from plural input/output channels to shared main storage. An address word in each request designates the identity of the source channel (CHID) and "destination" address (of a doubleword space in storage relative to which one, two or four "data" words shall be transferred). EOT tag signal provides demarcation of requests and also uniquely identifies "l-wide" input (Store) requests. Quadword (QW) tag, presented with "4-wide" requests, enables the storage access system to use a single address in the request to locate two contiguous doubleword spaces in storage. Data tags (Dl, D2), presented on a selective basis enable the access system to selectively steer (reorder the positions of) data words in an input request relative to word halves of the addressed space. Consequently the data repositioning function associated with Read Backward operations does not require reordering of data words in the channel buffers (saving handling time and expense of "steering" circuits in the individual channels). In association with a "l-wide" input request a single data tag, Dl or D2, is used to steer the single data word of the request into either half of the addressed space on a selective basis.

公开(公告)号：CA1089107A

公开(公告)日：1980-11-04

申请号：CA292260

申请日：1977-12-02

Applicant: IBM

Inventor： CAPOWSKI ROBERT S ,  WRIGHT LEWIS W ,  ZIMMERMAN TERRENCE K

IPC: G06F5/00 ,  G06F13/12 ,  G06F15/02 ,  G06F15/78 ,  G06F9/00

Abstract: CHANNEL BUS CONTROLLER The Channel Bus Controller (CBC) transfers information between groups of input/output channels and processor storage. Storage receives or dispenses two data words per access operation. Interfaces for transfers from the channel groups to the CBC are advantageously one word wide; since each output (fetch) request consists of a single request word. Information sent by each group is assembled into three-word units (a request word and zero, one or two data words) in a respective channel bus assembly register (CBAR). The assembled unit is passed from the CBAR to a respective area of an In Buffer array and from that array to storage. Zero filler words are inserted into unused data word positions. A channel request may be tagged to designate a transfer of four data words. If the transfer is an input the four data words are sent to the CBC with a single request word. The third and fourth data words are written in the CBAR over the first and second data words as (or after) the unit formed by the request and first and second data words is advanced to the In Buffer. The same request and the third and fourth data words are transferred as a second unit from the CBAR to the In Buffer. The low order bit in the address part of the request is inverted by the CBC to designate the "next" storage address. This saves time by eliminating a request unit transfer from the source channel group. Request transfers from a group are permitted when a vacancy exists either in the respective CBAR or in a respective area of the In Buffer. Outputs from storage (acknowledgments of data inputs and fetched/output data) are returned to the respective channel group via a respective area of an out suffer array. Returns to a group are ordered in the input sequence of respective requests to the CBC although the requests may be applied to storage in another sequence. Tags generated by the CBC are used to maintain the correct output order without delaying evacuation of the In Buffer. The area partitioning of the in and out buffer arrays provides balanced group access to storage and simplifies handling of group traffic. Channel identity information in the request words is looped through the buffer arrays and returned to the channel groups with respective outputs. This permits the CBC (and storage) to ignore channel origins of group traffic and thereby further simplifies handling of traffic.