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    4.
    发明专利
    未知

    公开(公告)号：DE2834869A1

    公开(公告)日：1979-05-31

    申请号：DE2834869

    申请日：1978-08-09

    Applicant: IBM

    Inventor： DAVIDSON ARTHUR ,  HERREL DENNIS JAMES

    IPC: G11C11/44 ,  H03K3/38 ,  H03K19/195 ,  H03K5/18

    Abstract: JOSEPHSON SELF GATING AND CIRCUIT AND LATCH CIRCUIT of the Invention A Josephson Self Gating And circuit which is powered by pulsed or clipped alternating current and provides true and complement outputs in response to true and complement inputs is disclosed. Inputs applied during the duration of the applied pulsed power or clipped alternating current are delivered to outputs which are maintained in that state in spite of a change of input within the given pulse duration. In one embodiment, the presence of an output signal interrupts a current path which, in turn, disables a pair of AND gates. These gates, even though the input to them changes, can provide no other output until the applied power falls to zero resetting the pair of AND gates which are latching in character. In another embodiment, current paths of one AND gate are cross-coupled with a current path of another AND gate. The interruption of current in a serially disposed Josephson device in one or the other of the current paths disables one or the other of the pair of AND gates preventing a change in outputs until the next cycle of applied pulsed or alternating current power. A latch circuit incorporating a pair of AND gates, a flip-flop and a Self Gating And circuit is also disclosed. The latch permits an input different from a previously applied input to the flip-flop to change the state of the flip-flop without changing the output of the Self Gating And during the application of a cycle of pulsed or alternating current power. The changed input to the flip-flop appears at the output of the Self Gating And circuit during the next cycle of applied pulsed or alternating current power. YO977-035 - 1

    HIGH CURRENT CONDUCTORS AND HIGH FIELD MAGNETS USING ANISOTROPIC SUPERCONDUCTORS
    5.
    发明专利
    HIGH CURRENT CONDUCTORS AND HIGH FIELD MAGNETS USING ANISOTROPIC SUPERCONDUCTORS 未知

    公开(公告)号：CA1331480C

    公开(公告)日：1994-08-16

    申请号：CA566244

    申请日：1988-05-06

    Applicant: IBM

    Inventor： DAVIDSON ARTHUR ,  DINGER TIMOTHY R ,  GALLAGHER WILLIAM J ,  WORTHINGTON THOMAS K

    IPC: H01F6/06 ,  H01L39/14 ,  H01F7/22

    Abstract: HIGH CURRENT CONDUCTORS AND HIGH FIELD MAGNETS USING ANISOTROPIC SUPERCONDUCTORS Improved conductors and superconducting magnets are described utilizing superconducting materials exhibiting critical field anisotropy. This anisotropy is one in which the ability of the superconductor to stay in a superconducting state depends on the orientation of a magnetic field applied to the superconductor with respect to the direction of current flow in the superconductor. This anisotropy is utilized in the design of conductors and magnet windings comprising the superconductive material and specifically is directed to magnet windings in which the direction of high critical current through the superconductor is parallel to the magnetic field produced by current in these windings in order to obtain high critical fields. Particularly favorable examples of a superconducting material are the so-called high Tc superconductors in which the primary supercurrent flow is confined to 2 dimensional Cu-O planes. By arranging the superconductive windings so that the Cu-O planes are substantially parallel to the magnetic field produced by current in these windings, the windings will be able to withstand high fields without being driven normal. This maximizes the magnetic field amplitudes that can be produced by the magnet.

    ROOM TEMPERATURE CRYOGENIC TEST INTERFACE
    7.
    发明专利
    ROOM TEMPERATURE CRYOGENIC TEST INTERFACE 未知

    公开(公告)号：CA1194610A

    公开(公告)日：1985-10-01

    申请号：CA435248

    申请日：1983-08-24

    Applicant: IBM

    Inventor： FARIS SADEG M ,  MOSKOWITZ PAUL A ,  DAVIDSON ARTHUR ,  SAI-HALASZ GEORGE A

    IPC: H01L39/24 ,  F17C13/00 ,  G01R13/34 ,  G01R31/28 ,  G01R31/26

    Abstract: ROOM TEMPERATURE CRYOGENIC TEST INTERFACE This interface permits the testing of high speed semiconductor devices (room-temperature chips) by a Josephson junction sampling device (cryogenic chip) without intolerable loss of resolution. The interface comprises a quartz pass-through plug which includes a planar transmission line interconnecting a first chip station, where the cryogenic chip is mounted, and a second chip station, where the semiconductor chip to be tested is temporarily mounted. The pass-through plug has a cemented long half-cylindrical portion and short half-cylindrical portion. The long portion carries the planar transmission line, the ends of which form the first and second chip mounting stations. The short portion completes the cylinder with the long portion for part of its length, where a seal can be achieved, but does not extend over the chip mounting stations. Sealing is by epoxy cement. The pass-through plug is sealed in place in a flange mounted to the chamber wall. The first chip station, with the cryogenic chip attached, extends into the liquid helium reservoir. The second chip station is in the room temperature environment required for semiconductor operation. Proper semiconductor operating temperature is achieved by a heater wire and control thermocouple in the vicinity of each other and the second chip mounting station. Thermal isolation is maintained by vacuum and seals. Connections for power and control, for test result signals, for temperature control and heating, and for vacuum complete the test apparatus.

    JOSEPHSON SELF GATING AND CIRCUIT AND LATCH CIRCUIT
    8.
    发明专利
    JOSEPHSON SELF GATING AND CIRCUIT AND LATCH CIRCUIT 未知

    公开(公告)号：CA1099344A

    公开(公告)日：1981-04-14

    申请号：CA305438

    申请日：1978-06-14

    Applicant: IBM

    Inventor： DAVIDSON ARTHUR ,  HERRELL DENNIS J

    IPC: G11C11/44 ,  H03K3/38 ,  H03K19/195

    Abstract: JOSEPHSON SELF GATING AND CIRCUIT AND LATCH CIRCUIT of the Invention A Josephson Self Gating And circuit which is powered by pulsed or clipped alternating current and provides true and complement outputs in response to true and complement inputs is disclosed. Inputs applied during the duration of the applied pulsed power or clipped alternating current are delivered to outputs which are maintained in that state in spite of a change of input within the given pulse duration. In one embodiment, the presence of an output signal interrupts a current path which, in turn, disables a pair of AND gates. These gates, even though the input to them changes, can provide no other output until the applied power falls to zero resetting the pair of AND gates which are latching in character. In another embodiment, current paths of one AND gate are cross-coupled with a current path of another AND gate. The interruption of current in a serially disposed Josephson device in one or the other of the current paths disables one or the other of the pair of AND gates preventing a change in outputs until the next cycle of applied pulsed or alternating current power. A latch circuit incorporating a pair of AND gates, a flip-flop and a Self Gating And circuit is also disclosed. The latch permits an input different from a previously applied input to the flip-flop to change the state of the flip-flop without changing the output of the Self Gating And during the application of a cycle of pulsed or alternating current power. The changed input to the flip-flop appears at the output of the Self Gating And circuit during the next cycle of applied pulsed or alternating current power. YO977-035 - 1

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