公开(公告)号：AU1672500A

公开(公告)日：2000-07-03

申请号：AU1672500

申请日：1999-12-10

Applicant: IBM ,  IBM UK

Inventor： BAUMGARTNER YOANNA ,  DEAN MARK EDWARD ,  ELMAN ANNA

IPC: G06F12/00 ,  G06F12/08 ,  G06F15/16

Abstract: A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes a local interconnect, a processor and a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In response to receipt of a read request from the local interconnect, the node controller speculatively transmits the read request to the remote processing node via the node interconnect. Thereafter, in response to receipt of a response to the read request from the remote processing node, the node controller handles the response in accordance with a resolution of the read request at the local processing node. For example, in one processing scenario, data contained in the response received from the remote processing node is discarded by the node controller if the read request received a Modified Intervention coherency response at the local processing node.

公开(公告)号：PL348859A1

公开(公告)日：2002-06-17

申请号：PL34885999

申请日：1999-12-10

Applicant: IBM ,  IBM UK

Inventor： BAUMGARTNER YOANNA ,  DEAN MARK EDWARD ,  ELMAN ANNA

IPC: G06F12/08 ,  G06F12/00 ,  G06F15/16

Abstract: A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes a local interconnect, a processor and a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In response to receipt of a read request from the local interconnect, the node controller speculatively transmits the read request to the remote processing node via the node interconnect. Thereafter, in response to receipt of a response to the read request from the remote processing node, the node controller handles the response in accordance with a resolution of the read request at the local processing node. For example, in one processing scenario, data contained in the response received from the remote processing node is discarded by the node controller if the read request received a Modified Intervention coherency response at the local processing node.

公开(公告)号：HU0104577A2

公开(公告)日：2002-03-28

申请号：HU0104577

申请日：1999-12-10

Applicant: IBM UK ,  IBM

Inventor： BAUMGARTNER YOANNA ,  DEAN MARK EDWARD ,  ELMAN ANNA

IPC: G06F12/00 ,  G06F12/08 ,  G06F15/16

Abstract: A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes a local interconnect, a processor and a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In response to receipt of a read request from the local interconnect, the node controller speculatively transmits the read request to the remote processing node via the node interconnect. Thereafter, in response to receipt of a response to the read request from the remote processing node, the node controller handles the response in accordance with a resolution of the read request at the local processing node. For example, in one processing scenario, data contained in the response received from the remote processing node is discarded by the node controller if the read request received a Modified Intervention coherency response at the local processing node.

公开(公告)号：AT236431T

公开(公告)日：2003-04-15

申请号：AT99959592

申请日：1999-12-10

Applicant: IBM

Inventor： BAUMGARTNER YOANNA ,  DEAN MARK EDWARD ,  ELMAN ANNA

IPC: G06F12/00 ,  G06F12/08 ,  G06F15/16

Abstract: A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes a local interconnect, a processor and a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In response to receipt of a read request from the local interconnect, the node controller speculatively transmits the read request to the remote processing node via the node interconnect. Thereafter, in response to receipt of a response to the read request from the remote processing node, the node controller handles the response in accordance with a resolution of the read request at the local processing node. For example, in one processing scenario, data contained in the response received from the remote processing node is discarded by the node controller if the read request received a Modified Intervention coherency response at the local processing node.

公开(公告)号：IE990755A1

公开(公告)日：2000-05-03

申请号：IE990755

申请日：1999-09-07

Applicant: IBM

Inventor： GLASCO DAVID BRIAN ,  JNR RICHARD NICHOLAS IACHETTA ,  CARPENTER GARY DALE ,  DEAN MARK EDWARD

IPC: G06F15/163 ,  G06F12/08

Abstract: A non-uniform memory access (NUMA) data processing system includes a node interconnect to which at least a first processing node and a second processing node are coupled. The first and the second processing nodes each include a local interconnect, a processor coupled to the local interconnect, a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In order to reduce communication latency, the node controller of the first processing node speculatively transmits request transactions received from the local interconnect of the first processing node to the second processing node via the node interconnect. In one embodiment, the node controller of the first processing node subsequently transmits a status signal to the node controller of the second processing node in order to indicate how the request transaction should be processed at the second processing node.

公开(公告)号：DE69030688D1

公开(公告)日：1997-06-19

申请号：DE69030688

申请日：1990-06-11

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F13/36 ,  G06F13/28 ,  G06F13/362 ,  G06F13/364

Abstract: A logic circuit external to a microprocessor monitors selected processor I/O pins to determine the current processor cycle and, in response to a hold request signal, drives the processor into a hold state at the appropriate time in the cycle. The logic circuit also includes a "lockbus" feature that, when the processor is not idle, "locks" the microprocessor to the local CPU bus for a predetermined period of time immediately after the processor is released from a hold state.

公开(公告)号：IN177313B

公开(公告)日：1996-12-28

申请号：IN628DE1989

申请日：1989-07-13

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD ,  GAUDENZI GENE JOSEPH ,  KRAMER KEVIN GERRARD ,  TEMPEST SUSAN LYNN

IPC: G06F7/00

公开(公告)号：FI96145C

公开(公告)日：1996-05-10

申请号：FI891786

申请日：1989-04-14

Applicant: IBM

Inventor： MILLING PHILIP ERNA ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F9/44 ,  G06F9/445 ,  G06F13/36 ,  G06F13/362

公开(公告)号：DE68923403T2

公开(公告)日：1996-03-07

申请号：DE68923403

申请日：1989-03-03

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G11C11/401 ,  G06F13/36 ,  G06F13/362 ,  G11C7/10 ,  G11C7/00

Abstract: A computer system includes a page memory in which a row address accompanied by a row address strobe (RAS) is followed by a column address accompanied by a column address strobe (CAS) to read data from a memory location during a memory cycle. When, in a following memory cycle, a further location from the same page is to be accessed, the row address and the RAS remain constant and a new column address is used with the CAS being precharged by switching it to its OFF state and then returning it to its ON state. This is normally done at the start of the following memory cycle. In the present system, the data is read and latched shortly after arrival of the column address and CAS in the first of the memory cycles so that the CAS recharge can take place at the end of the first memory cycle and before the start of the following memory cycle.

公开(公告)号：FI95971B

公开(公告)日：1995-12-29

申请号：FI891784

申请日：1989-04-14

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G11C11/401 ,  G06F13/36 ,  G06F13/362 ,  G11C7/10 ,  G06F12/00 ,  G11C7/00

Abstract: A computer system includes a page memory in which a row address accompanied by a row address strobe (RAS) is followed by a column address accompanied by a column address strobe (CAS) to read data from a memory location during a memory cycle. When, in a following memory cycle, a further location from the same page is to be accessed, the row address and the RAS remain constant and a new column address is used with the CAS being precharged by switching it to its OFF state and then returning it to its ON state. This is normally done at the start of the following memory cycle. In the present system, the data is read and latched shortly after arrival of the column address and CAS in the first of the memory cycles so that the CAS recharge can take place at the end of the first memory cycle and before the start of the following memory cycle.