中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

15 records (took 0.017 seconds)

    Base-to-emitter compensation for current switch emitter-follower circuits
    2.
    发明授权
    Base-to-emitter compensation for current switch emitter-follower circuits 失效
    电流开关电源电路的基极发生器补偿

    公开(公告)号：US3636384A

    公开(公告)日：1972-01-18

    申请号：US3636384D

    申请日：1970-09-14

    Applicant: IBM

    Inventor： DEWITT DAVID

    IPC: H03K17/14 ,  H03K17/60 ,  H03K19/086 ,  H03K1/12

    CPC classification number: H03K17/603 ,  H03K17/14 ,  H03K19/086

    Abstract: A current-switch emitter-follower is provided with a circuit which compensates for the variations in base-to-emitter voltage due to variations in temperature. The circuit comprises a regulated power supply which maintains its output at a predetermined level with respect to a reference potential such as ground. The power supply includes a transistor having its emitter at said reference potential. The base of this transistor is connected to the power supply output terminal which is therefore maintained at a predetermined level, the base-to-emitter voltage, with respect to said ground reference potential. The base-toemitter voltage of this transistor tracks the base-to-emitter voltage of the emitter-follower circuits so as to compensate for the variations in the latter.

    PROTON ENHANCED DIFFUSION DEVICES AND METHODS
    5.
    发明专利
    PROTON ENHANCED DIFFUSION DEVICES AND METHODS 未知

    公开(公告)号：CA974661A

    公开(公告)日：1975-09-16

    申请号：CA159099

    申请日：1972-12-14

    Applicant: IBM

    Inventor： AHN JUNGHI ,  DEWITT DAVID ,  JOHNSON WILLIAM S ,  KLEINFELDER WALTER J

    IPC: H01L23/52 ,  H01J37/317 ,  H01L21/265 ,  H01L21/3205 ,  H01L21/331 ,  H01L21/76 ,  H01L21/761 ,  H01L21/8228 ,  H01L27/00 ,  H01L27/06 ,  H01L29/73

    Abstract: 1415500 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 30 Nov 1972 [21 Dec 1971] 55226/72 Heading H1K A method of outdiffusing impurities from a doped region within a semi-conductor body to other parts of the body comprises bombarding the body surface with a beam of ions having a mass number not greater than four while heating the body; the beam causing lattice vacancies to occur, at the part of the region where out diffusion is desired, so enhancing the diffusivity of the impurities at said part. The preferred ions are those of hydrogen or helium, which do not cause the sufficient crystal damage to increase the bulk resistivity of the body. The beam may be applied to the body through a mask on the surface thereof or by a narrow focused beam and the energy of the ions may be reduced during bombardment to lead the impurities towards the body surface. The out diffusion may be used to form a pedestal portion from a buried collector region of a transistor, the ion beam passing through the emitter aperture to ensure alignment of the pedestal portion and the emitter. The ion beam may also be used to form interconnections from regions buried deep in the body prior to epitaxial deposition. The body may be of silicon with arsenic and boron dopants; being heated during bombardment. Aluminium or molybdenum may be used for electrode material. A pedestal transistor (Fig. 3b) comprises a substrate wafer 2 of P-type B doped Si with an N-type epitaxial layer 10; a sub-collector 8 being As diffused into the substrate prior to growth of layer 10 and further out diffused during growth to form a new sub-collector region 14. A B diffused P-type base 22 and an A s diffused N-type emitter 26 are located in the surface of layer 10; and Fig. 3a shows the impurity contour 62 of the A s emitter diffusion, contour 64 of the B diffusion of the base and the intersection 66 of the emitter base junction. Contour 69 of the out diffused sub-collector region 14 does not intersect base contour 64. A collector pedestal from out diffused region 14 up to the base region underlying emitter 26 is grown by focusing an ionic beam on to the emitter site; the wafer being heated with propressive reduction of the beam acceleration voltage so that the locus of the impurities approaches the wafer surface to vary the contour of the impurity concentration profile to that of contour 70 (Fig. 3a). The ionic beam may impinge on an apertured surface masking layer with a perforation at the emitter site, and a substrate 2 is thermally oxidized to form layers 4, 6 (Fig. 4b). A subcollector window is open in layer 6 into which a N+ type sub-collector region 8 is thermally diffused with A s during which layer 6 is regrown. Windows are again opened and a P-type isolation sub-region is in-diffused with B. Layer 6 is removed and N-type epitaxial layer 10 is grown on substrate 2, on which a new SiO 2 layer is formed and N + type region 8 is out diffused into sub-collector region 14 while P-type region 9 is outdiffused into P-type region 16 (Fig. 4d). Windows are opened in layer 12 and P-type isolation and base regions 20, 22 are thermally in-diffused using B. Oxide mask 12 is regrown during the thermal drive in and windows are etched thereon through which N + type emitter region 26 and N+ sub-collector reach through region 28 are in-diffused using A s ; at the same time regions 16, 20 out diffusing to form isolation regions 32 (Fig. 4f). The wafer is placed in an irradiation chamber of an ion acceleration system (Fig. 5, not shown) and heated to a stable temperature after which the beam is directed on the wafer (masked by layer 12) at a preset acceleration voltage which is decreased linearly with time, and during bombardment A s outgrows from region 14 to a critical concentration and position underlying the surface at base 22 and reach through region 28 to form a basecollector PN junction for the pedestal transistor. After bombardment is completed the wafer is removed and cooled and the SiO 2 mask 12 regrown. Enhanced diffusion parameters are variable over a wide range and the masks may alternatively be of molybdenum, aluminium, or gold, while the projectile ions may be hydrogen, deuterium, diatomic hydrogen, tritium, helium 3, helium 4, or admixtures thereof. The ions may be focused in a narrow beam without masking. In a modified process for fabricating pedestal transistors by ionic enhanced diffusion, plural transistor pedestals are induced to grow to different heights simultaneously in a single operation utilizing an ionic attenuator of, e.g. molybdenum placed in a bombardment window (Fig. 6, not shown) and the process may be used to fabricate pedestal transistors in combination with diffusion capacitors in multilayer monolithic circuits (Figs. 7a to 7e, not shown) with sub-surface diffused networks of electrical connectors incorporated in the substrate, which are fabricated by thermal diffusion from a buried matrix of heavily doped impurity regions enhanced by masked ionic bombardment (Figs. 8a to 8g, not shown). Reference has been directed by the Comptroller to Specifications 1,307,546 and 1,320,555.

    7.
    发明专利
    未知

    公开(公告)号：DE2657643A1

    公开(公告)日：1977-07-14

    申请号：DE2657643

    申请日：1976-12-20

    Applicant: IBM

    Inventor： CHRISTIE KENNETH HOWARD ,  DEWITT DAVID ,  JOHNSON WILLIAM STANFORD

    IPC: H01L21/8247 ,  G11C16/04 ,  H01L21/336 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

    Abstract: A metal nitride oxide semiconductor device capable of use within a memory cell, having a more heavily doped region of the same type as the substrate provided directly under the channel of the depletion mode device. Application of a positive write voltage to the gate of the device, with the substrate at 0 volts potential and the source and drain biased to a suitable positive level, results in avalanche operation of the device whereby charge is stored in a nitride oxide interface under the gate, thereby converting the device to enhancement mode operation. The charge can be removed with the source and drain biased to the 0 volt potential of the substrate and a positive erase signal applied to the gate. A four device memory cell is disclosed.

Patent Agency Ranking