公开(公告)号：WO2011113661A3

公开(公告)日：2011-11-17

申请号：PCT/EP2011052431

申请日：2011-02-18

Applicant: IBM ,  IBM UK ,  SHEDIVY DAVID ALAN ,  HILLIER III PHILIP ROGERS ,  VALK KENNETH MICHAEL ,  FLYNN WILLIAM THOMAS

Inventor： SHEDIVY DAVID ALAN ,  HILLIER III PHILIP ROGERS ,  VALK KENNETH MICHAEL ,  FLYNN WILLIAM THOMAS

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4022 ,  G06F2213/0026

Abstract: A method and circuit for implementing ordered and reliable transfer of packets while spraying packets over multiple links, and a design structure on which the subject circuit resides are provided. Each source interconnect chip maintains a spray mask including multiple available links for each destination chip for spraying packets across multiple links of a local rack interconnect system. Each packet is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The destination interconnect chip uses the ETE sequence numbers to reorder the received sprayed packets into the correct order before sending the packets to the destination device.

Abstract translation: 一种用于在通过多个链路喷射分组时实现分组的有序和可靠传送的方法和电路，并且提供了主题电路所在的设计结构。 每个源互连芯片保持喷射掩模，其包括用于每个目的地芯片的多个可用链路，用于在本地机架互连系统的多个链路上喷射分组。 每个数据包被分配在源互连芯片中的端到端（ETE）序列号，其表示来自源设备的有序分组流中的分组位置。 目的互连芯片在将数据包发送到目标设备之前，使用ETE序列号将接收到的喷射数据包重新排序为正确的顺序。

公开(公告)号：HU0100013A2

公开(公告)日：2001-05-28

申请号：HU0100013

申请日：1998-10-14

Applicant: IBM

Inventor： BORKENHAGEN JOHN MICHAEL ,  EICKEMEYER RICHARD JAMES ,  FLYNN WILLIAM THOMAS ,  LEVENSTEIN SHELDON BERNARD ,  WOTTRENG ANDREW HENRY

IPC: G06F12/08 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48

Abstract: A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

公开(公告)号：CZ20001437A3

公开(公告)日：2000-07-12

申请号：CZ20001437

申请日：1998-10-14

Applicant: IBM

Inventor： BORKENHAGEN JOHN MICHAEL ,  EICKEMEYER RICHARD JAMES ,  FLYNN WILLIAM THOMAS ,  LEVENSTEIN SHELDON BERNARD ,  WOTTRENG ANDREW HENRY

IPC: G06F9/38 ,  G06F9/46

公开(公告)号：DE112011100164T5

公开(公告)日：2012-10-04

申请号：DE112011100164

申请日：2011-02-18

Applicant: IBM

Inventor： SHEDIVY DAVID ALAN ,  VALK KENNETH MICHAEL ,  FLYNN WILLIAM THOMAS ,  HILLIER III PHILIP ROGERS

IPC: G06F13/42 ,  G06F13/40

Abstract: Ein Verfahren und eine Schaltung zum Umsetzen einer geordneten und zuverlässigen Übertragung von Datenpaketen, wobei Pakete über mehrere Verbindungen verteilt werden, und eine Konzeptionsstruktur, auf der die betreffende Schaltung aufgebracht ist, werden bereitgestellt. Jeder Quell-Verbindungs-Chip hält eine Verteilermaske bereit, die mehrere verfügbare Verbindungen für jeden Ziel-Chip enthält, um Datenpakete über mehrere Verbindungen eines Verbindungssystems mit lokalem Rack zu verteilen. Jedem Datenpaket wird in dem Quell-Verbindungs-Chip eine Versandreihenfolgenummer (End-to-End, ETE sequence number) zugewiesen, die die Paketposition in einem von der Quelleinheit ausgehenden geordneten Paketstrom wiedergibt. Der Ziel-Verbindungs-Chip verwendet die ETE-Reihenfolgenummern, um die empfangenen verteilten Pakete in der zutreffenden Reihenfolge neu zu ordnen, bevor die Pakete an die Zieleinheit versendet werden.

公开(公告)号：CA2299348C

公开(公告)日：2004-10-19

申请号：CA2299348

申请日：1998-10-14

Applicant: IBM

Inventor： WOTTRENG ANDREW HENRY ,  BORKENHAGEN JOHN MICHAEL ,  FLYNN WILLIAM THOMAS ,  EICKEMEYER RICHARD JAMES

IPC: G06F12/08 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48

Abstract: A system and method for performing computer processing operations in a data processing system (10) includes a multithreaded processor (100) and thread switch logic (400). The multithreaded processor is capable of switching between two or more threads of instractions which can be independently executed. Each thread has a corresponding state in a thread state register (440) depending on its execution status. The thread switch logic contains a thread switch control register (410) to store the conditions upon which a thread will occur. The thread switch logic has a time-out register (430) which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register (420) to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager (460) capable of changing the priority of the different threads and thus superseding thread switch events.

公开(公告)号：GB2512015A

公开(公告)日：2014-09-24

申请号：GB201209549

申请日：2011-02-18

Applicant: IBM

Inventor： SHEDIVY DAVID ALAN ,  HILLIER PHILIP ROGERS III ,  VALK KENNETH MICHAEL ,  FLYNN WILLIAM THOMAS

IPC: G06F13/40

Abstract: A method and circuit for implementing ordered and reliable transfer of packets while spraying packets over multiple links, and a design structure on which the subject circuit resides are provided. Each source interconnect chip maintains a spray mask including multiple available links for each destination chip for spraying packets across multiple links of a local rack interconnect system. Each packet is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The destination interconnect chip uses the ETE sequence numbers to reorder the received sprayed packets into the correct order before sending the packets to the destination device.

公开(公告)号：PL193285B1

公开(公告)日：2007-01-31

申请号：PL34009598

申请日：1998-10-14

Applicant: IBM

Inventor： BORKENHAGEN JOHN MICHAEL ,  EICKEMEYER RICHARD JAMES ,  FLYNN WILLIAM THOMAS ,  WOTTRENG ANDREW HENRY

IPC: G06F9/38 ,  G06F12/08 ,  G06F9/46 ,  G06F9/48

公开(公告)号：DE112011100164B4

公开(公告)日：2017-03-23

申请号：DE112011100164

申请日：2011-02-18

Applicant: IBM

Inventor： SHEDIVY DAVID ALAN ,  VALK KENNETH MICHAEL ,  FLYNN WILLIAM THOMAS ,  HILLIER III PHILIP ROGERS

IPC: G06F13/42 ,  G06F13/40

Abstract: Ein Verfahren und eine Schaltung zum Umsetzen einer geordneten und zuverlässigen Übertragung von Datenpaketen, wobei Pakete über mehrere Verbindungen verteilt werden, und eine Konzeptionsstruktur, auf der die betreffende Schaltung aufgebracht ist, werden bereitgestellt. Jeder Quell-Verbindungs-Chip hält eine Verteilermaske bereit, die mehrere verfügbare Verbindungen für jeden Ziel-Chip enthält, um Datenpakete über mehrere Verbindungen eines Verbindungssystems mit lokalem Rack zu verteilen. Jedem Datenpaket wird in dem Quell-Verbindungs-Chip eine Versandreihenfolgenummer(End-to-End, ETE sequence number)zugewiesen, die die Paketposition in einem von der Quelleinheit ausgehenden geordneten Paketstrom wiedergibt. Der Ziel-Verbindungs-Chip verwendet die ETE-Reihenfolgenummern, um die empfangenen verteilten Pakete in der zutreffenden Reihenfolge neu zu ordnen, bevor die Pakete an die Zieleinheit versendet werden.

公开(公告)号：GB2324392B

公开(公告)日：2001-09-05

申请号：GB9803618

申请日：1998-02-23

Applicant: IBM

Inventor： FLYNN WILLIAM THOMAS ,  HILLIER III PHILIP ROGERS

IPC: G06F9/38 ,  G06F9/46

Abstract: The method and apparatus for decreasing thread switch latency in a multithread processor stores instructions for an active thread in a primary instruction queue, and stores instructions for a dormant thread in a thread switch instruction queue. The active thread is the thread currently being processed by the multithread processor, while the dormant thread is a thread not currently being executed by the multithread processor. During execution of the active thread, instructions are dispatched from the primary instruction queue for processing. When a thread switch occurs, instructions are dispatched from the thread switch instruction queue for execution. Simultaneously, instructions stored in the thread switch instruction queue are transferred to the primary instruction queue. In this manner, the thread switch latency resulting from the amount of time to refill the primary instruction queue with instructions of the dormant thread is eliminated.

公开(公告)号：HK1011567A1

公开(公告)日：1999-07-16

申请号：HK98112653

申请日：1998-12-02

Applicant: IBM

Inventor： FLYNN WILLIAM THOMAS ,  HILLIER PHILIP ROGERS III

IPC: G06F9/38 ,  G06F9/46 ,  G06F

Abstract: The method and apparatus for decreasing thread switch latency in a multithread processor stores instructions for an active thread in a primary instruction queue, and stores instructions for a dormant thread in a thread switch instruction queue. The active thread is the thread currently being processed by the multithread processor, while the dormant thread is a thread not currently being executed by the multithread processor. During execution of the active thread, instructions are dispatched from the primary instruction queue for processing. When a thread switch occurs, instructions are dispatched from the thread switch instruction queue for execution. Simultaneously, instructions stored in the thread switch instruction queue are transferred to the primary instruction queue. In this manner, the thread switch latency resulting from the amount of time to refill the primary instruction queue with instructions of the dormant thread is eliminated.