公开(公告)号：US3569799A

公开(公告)日：1971-03-09

申请号：US3569799D

申请日：1967-01-13

Applicant: IBM

Inventor： FANG FRANK F ,  FOWLER ALAN B

IPC: H01L23/29 ,  H01L27/07 ,  H01L29/00 ,  H01L29/08 ,  H01L29/68 ,  H01L11/00

CPC classification number: H01L29/685 ,  H01L23/29 ,  H01L23/291 ,  H01L27/0788 ,  H01L29/00 ,  H01L29/0804 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This disclosure provides a control feature for a solid state device which has a negative resistance characteristic in the current-voltage curve due to an insulator in the current path. A negative resistance device is fabricated by planar technology to have an insulator layer interposed between a semiconductor layer and a metal layer in the negative resistance current path. The control feature is provided through a control electrode which has a lateral junction in the semiconductor layer and near to the current path through the insulator layer. Control voltage pulses of opposite polarities applied to the control electrode obtain switching between stable states of the device in both directions without a requirement of turning off the current.

公开(公告)号：US3509384A

公开(公告)日：1970-04-28

申请号：US39330364

申请日：1964-08-31

Applicant: IBM

Inventor： FOWLER ALAN B ,  LASHER GORDON J

IPC: G02F3/00 ,  G02F3/02 ,  H01S3/06 ,  H01S5/062 ,  H03K23/12 ,  H01S3/00

CPC classification number: H01S5/4006 ,  G02F3/00 ,  G02F3/026 ,  H01S5/06243

公开(公告)号：US3138713A

公开(公告)日：1964-06-23

申请号：US4382460

申请日：1960-07-19

Applicant: IBM

Inventor： FOWLER ALAN B

IPC: H03K3/42

CPC classification number: H03K3/42

公开(公告)号：US3679492A

公开(公告)日：1972-07-25

申请号：US3679492D

申请日：1970-03-23

Applicant: IBM

Inventor： FANG FRANK F ,  FOWLER ALAN B

IPC: H01L21/265 ,  H01L29/00 ,  H01L29/76 ,  H01L7/54

CPC classification number: H01L29/00 ,  H01L21/265 ,  H01L29/76 ,  Y10S148/053 ,  Y10S148/103 ,  Y10S148/105 ,  Y10S148/147

Abstract: A PROCESS FOR PREPARING METAL-OXIDE SEMICONDUCTOR DEVICES (MOSFET''S) USING ION IMPLANATION IS DESCRIBED WHEREIN ALUMINUM SOURCE AND DRAIN CONTACTS ARE ADDED AFTER ION IMPLANTATION THROUGH A HIGHLY REFRECATORY METAL GATE SO THAT VERY HIGH TEMPERATURE ANNEALING CAN BE USED. IF THE ALUMINUM CONTACTS ARE PUT DOWN BEFORE THE HIGH TEMPERATURE ANNEALING, NOT ONLY DOES A REACTION BETWEEN THE ALUMINUM AND THIN OXIDE CHANNEL REGION OF THE MOSFET OCCUR, BUT OHMIC CONTACTS AT THE SOURCE AND DRAIN DETERIORATE, RESULTING IN DEFECTIVE DEVIES.

公开(公告)号：US3303431A

公开(公告)日：1967-02-07

申请号：US34358864

申请日：1964-02-10

Applicant: IBM

Inventor： FOWLER ALAN B

IPC: G02F3/00 ,  H01S5/062 ,  H01S5/10 ,  H01S5/50

CPC classification number: H01S5/0622 ,  G02F3/00 ,  H01S5/10 ,  H01S5/1021 ,  H01S5/50

公开(公告)号：US3119986A

公开(公告)日：1964-01-28

申请号：US86320259

申请日：1959-12-31

Applicant: IBM

Inventor： FOWLER ALAN B

IPC: G11C11/44

CPC classification number: G11C11/44 ,  Y10S505/831

公开(公告)号：DE3880019T2

公开(公告)日：1993-10-28

申请号：DE3880019

申请日：1988-05-31

Applicant: IBM

Inventor： FOWLER ALAN B ,  FREEOUF JOHN L ,  KIRCHNER PETER D ,  WARREN ALAN C ,  WOODALL JERRY M

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/314 ,  H01L21/331 ,  H01L21/338 ,  H01L29/06 ,  H01L29/26 ,  H01L29/267 ,  H01L29/43 ,  H01L29/47 ,  H01L29/73 ,  H01L29/737 ,  H01L29/78 ,  H01L29/786 ,  H01L29/80 ,  H01L29/812 ,  H01L29/872 ,  H01L33/00 ,  H01L29/40 ,  H01L21/285

Abstract: A surface termination of a compound semiconductor is provided wherein conditions are provided for a pristine surface to be retained in an unpinned condition and a surface layer of a non-metallic material is provided. A GaAs substrate is heated in an oxygen-free atmosphere at high temperature with hydrogen sulfide, producing a pristine surface with a coating of gallium sulfide covered with a 1,000 nanometer covering of low temperature plasma enhanced chemical vapor deposited silicon dioxide.

公开(公告)号：DE3171523D1

公开(公告)日：1985-09-05

申请号：DE3171523

申请日：1981-01-23

Applicant: IBM

Inventor： CHAUDHARI PRAVEEN ,  CHOU NED J ,  FEDER RALPH ,  FOWLER ALAN B ,  VANVECHTEN JAMES A

IPC: G03F1/20 ,  H01L21/203 ,  H01L21/266 ,  C30B23/04 ,  G03F1/00

Abstract: A high aspect ratio collimating mask (2) for use in ion beam epitaxy or ion implantation doping is formed through the use of damage-trail-forming materials which are irradiated through a mask and then etched. The high aspect ratio is obtained in part by the sequential formation of a plurality of spaced mask plates. The mask is useful in producing large scale integrated circuits by localized ion implantation (10) during epitaxial growth (7) of a crystal wafer (1). In apparatus for use of the collimating mask (2), the crystal wafer (1) is held perpendicular to the plurality of discrete parallel ion beams (10) emitted through the collimating mask (2).

公开(公告)号：CA849749A

公开(公告)日：1970-08-18

申请号：CA849749D

Applicant: IBM

Inventor： FANG FRANK F ,  FOWLER ALAN B

公开(公告)号：DE3880019D1

公开(公告)日：1993-05-13

申请号：DE3880019

申请日：1988-05-31

Applicant: IBM

Inventor： FOWLER ALAN B ,  FREEOUF JOHN L ,  KIRCHNER PETER D ,  WARREN ALAN C ,  WOODALL JERRY M

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/314 ,  H01L21/331 ,  H01L21/338 ,  H01L29/06 ,  H01L29/26 ,  H01L29/267 ,  H01L29/43 ,  H01L29/47 ,  H01L29/73 ,  H01L29/737 ,  H01L29/78 ,  H01L29/786 ,  H01L29/80 ,  H01L29/812 ,  H01L29/872 ,  H01L33/00 ,  H01L29/40 ,  H01L21/285

Abstract: A surface termination of a compound semiconductor is provided wherein conditions are provided for a pristine surface to be retained in an unpinned condition and a surface layer of a non-metallic material is provided. A GaAs substrate is heated in an oxygen-free atmosphere at high temperature with hydrogen sulfide, producing a pristine surface with a coating of gallium sulfide covered with a 1,000 nanometer covering of low temperature plasma enhanced chemical vapor deposited silicon dioxide.