公开(公告)号：ES2075837T3

公开(公告)日：1995-10-16

申请号：ES89110424

申请日：1989-06-09

Applicant: IBM

Inventor： CHISHOLM MATTHEW F ,  KIRCHNER PETER D ,  WARREN ALAN C ,  WOODALL JERRY M

IPC: C30B25/02 ,  C30B29/40 ,  C30B29/68 ,  H01L21/20 ,  H01L21/203 ,  H01L29/201

Abstract: Heterostructures (20) having a large lattice mismatch between an upper epilayer (24) and a substrate (22) and a method of forming such structures having a thin intermediate layer (26) are disclosed. The strain due to a lattice mismatch between the intermediate layer (26) and the substrate (22) is partially relieved by the formation of edge type dislocations (15) which are localized and photoelectrically inactive. Growth of the intermediate layer (26) is interrupted before it reaches the thickness at which the left over strain is relieved by 60 degree type threading dislocations. The upper epilayer (24) is then grown in an unstrained and defect-free condition upon the intermediate layer (26) where the unstrained lattice constant (aL2) of the epilayer (24) is about the same as the partially relieved strain lattice constant (aL1) of the intermediate layer (26). An unstrained defect-free epilayer (24) of InGaAs has been grown on a GaAs substrate (22) with an intermediate layer (26) 3-10 nm in thickness of InAs. Other large mismatch systems are disclosed, including, GaAs on Si with an intermediate layer (26) of GaInAs.

公开(公告)号：DE68923920D1

公开(公告)日：1995-09-28

申请号：DE68923920

申请日：1989-06-09

Applicant: IBM

Inventor： CHISHOLM MATTHEW F ,  KIRCHNER PETER D ,  WARREN ALAN C ,  WOODALL JERRY M

IPC: C30B25/02 ,  C30B29/40 ,  C30B29/68 ,  H01L21/20 ,  H01L21/203 ,  H01L29/201

Abstract: Heterostructures (20) having a large lattice mismatch between an upper epilayer (24) and a substrate (22) and a method of forming such structures having a thin intermediate layer (26) are disclosed. The strain due to a lattice mismatch between the intermediate layer (26) and the substrate (22) is partially relieved by the formation of edge type dislocations (15) which are localized and photoelectrically inactive. Growth of the intermediate layer (26) is interrupted before it reaches the thickness at which the left over strain is relieved by 60 degree type threading dislocations. The upper epilayer (24) is then grown in an unstrained and defect-free condition upon the intermediate layer (26) where the unstrained lattice constant (aL2) of the epilayer (24) is about the same as the partially relieved strain lattice constant (aL1) of the intermediate layer (26). An unstrained defect-free epilayer (24) of InGaAs has been grown on a GaAs substrate (22) with an intermediate layer (26) 3-10 nm in thickness of InAs. Other large mismatch systems are disclosed, including, GaAs on Si with an intermediate layer (26) of GaInAs.

公开(公告)号：DE3880019D1

公开(公告)日：1993-05-13

申请号：DE3880019

申请日：1988-05-31

Applicant: IBM

Inventor： FOWLER ALAN B ,  FREEOUF JOHN L ,  KIRCHNER PETER D ,  WARREN ALAN C ,  WOODALL JERRY M

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/314 ,  H01L21/331 ,  H01L21/338 ,  H01L29/06 ,  H01L29/26 ,  H01L29/267 ,  H01L29/43 ,  H01L29/47 ,  H01L29/73 ,  H01L29/737 ,  H01L29/78 ,  H01L29/786 ,  H01L29/80 ,  H01L29/812 ,  H01L29/872 ,  H01L33/00 ,  H01L29/40 ,  H01L21/285

Abstract: A surface termination of a compound semiconductor is provided wherein conditions are provided for a pristine surface to be retained in an unpinned condition and a surface layer of a non-metallic material is provided. A GaAs substrate is heated in an oxygen-free atmosphere at high temperature with hydrogen sulfide, producing a pristine surface with a coating of gallium sulfide covered with a 1,000 nanometer covering of low temperature plasma enhanced chemical vapor deposited silicon dioxide.

公开(公告)号：CA1238719A

公开(公告)日：1988-06-28

申请号：CA503081

申请日：1986-03-03

Applicant: IBM

Inventor： FREEOUF JOHN L ,  JACKSON THOMAS N ,  KIRCHNER PETER D

IPC: H01L29/812 ,  H01L21/338 ,  H01L27/10 ,  H01L29/205 ,  H01L29/778 ,  H01L29/80 ,  G11C11/40

Abstract: YO984-085 REVERSIBLE CHARGE STORAGE FLOATING GATE HETEROJUNCTION DEVICE A semiconductor storage device provides reversible control of conduction in a band offset heterojunction field effect transistor by providing an asymmetric barrier controlled charge storage capability that can position a potential well across the Fermi level to produce conduction and away from the Fermi level for a non-conducting condition and to retain that position in the absence of a signal. A GaAs channel FET with a multilayer gate of in order of proximity to the GaAs channel a gate layer of GaAlAs, a storage layer of GaAs, an asymmetric barrier layer of GaAlAs graded toward the GaAs storage layer and an ohmic adapting layer of GaAs.

公开(公告)号：DE68923920T2

公开(公告)日：1996-04-18

申请号：DE68923920

申请日：1989-06-09

Applicant: IBM

Inventor： CHISHOLM MATTHEW F ,  KIRCHNER PETER D ,  WARREN ALAN C ,  WOODALL JERRY M

IPC: C30B25/02 ,  C30B29/40 ,  C30B29/68 ,  H01L21/20 ,  H01L21/203 ,  H01L29/201

Abstract: Heterostructures (20) having a large lattice mismatch between an upper epilayer (24) and a substrate (22) and a method of forming such structures having a thin intermediate layer (26) are disclosed. The strain due to a lattice mismatch between the intermediate layer (26) and the substrate (22) is partially relieved by the formation of edge type dislocations (15) which are localized and photoelectrically inactive. Growth of the intermediate layer (26) is interrupted before it reaches the thickness at which the left over strain is relieved by 60 degree type threading dislocations. The upper epilayer (24) is then grown in an unstrained and defect-free condition upon the intermediate layer (26) where the unstrained lattice constant (aL2) of the epilayer (24) is about the same as the partially relieved strain lattice constant (aL1) of the intermediate layer (26). An unstrained defect-free epilayer (24) of InGaAs has been grown on a GaAs substrate (22) with an intermediate layer (26) 3-10 nm in thickness of InAs. Other large mismatch systems are disclosed, including, GaAs on Si with an intermediate layer (26) of GaInAs.

公开(公告)号：CA1330194C

公开(公告)日：1994-06-14

申请号：CA600745

申请日：1989-05-25

Applicant: IBM

Inventor： CHISHOLM MATTHEW F ,  KIRCHNER PETER D ,  WARREN ALAN C ,  WOODALL JERRY M

IPC: C30B25/02 ,  C30B29/40 ,  C30B29/68 ,  H01L21/20 ,  H01L21/203 ,  H01L29/201 ,  C30B29/10

Abstract: Heterostructures having a large lattice mismatch between an upper epilayer and a substrate and a method of forming such structures having a thin intermediate layer are disclosed. The strain due to a lattice mismatch between the intermediate layer and the substrate is partially relieved by the formation of edge type dislocations which are localized and photoelectrically inactive. Growth of the intermediate layer is interrupted before it reaches the thickness at which the left over strain is relieved by 60 degree type threading dislocations. The upper epilayer is then grown in an unstrained and defect-free condition upon the intermediate layer where the unstrained lattice constant of the epilayer is about the same as the partially relieved strain lattice constant of the intermediate layer. An unstrained defect-free epilayer of InGaAs has been grown on a GaAs substrate with an intermediate layer 3-10 nm in thickness of InAs. Other large mismatch systems are disclosed, including, GaAs on Si with an intermediate layer of GaInAs.

公开(公告)号：DE3880019T2

公开(公告)日：1993-10-28

申请号：DE3880019

申请日：1988-05-31

Applicant: IBM

Inventor： FOWLER ALAN B ,  FREEOUF JOHN L ,  KIRCHNER PETER D ,  WARREN ALAN C ,  WOODALL JERRY M

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/314 ,  H01L21/331 ,  H01L21/338 ,  H01L29/06 ,  H01L29/26 ,  H01L29/267 ,  H01L29/43 ,  H01L29/47 ,  H01L29/73 ,  H01L29/737 ,  H01L29/78 ,  H01L29/786 ,  H01L29/80 ,  H01L29/812 ,  H01L29/872 ,  H01L33/00 ,  H01L29/40 ,  H01L21/285

Abstract: A surface termination of a compound semiconductor is provided wherein conditions are provided for a pristine surface to be retained in an unpinned condition and a surface layer of a non-metallic material is provided. A GaAs substrate is heated in an oxygen-free atmosphere at high temperature with hydrogen sulfide, producing a pristine surface with a coating of gallium sulfide covered with a 1,000 nanometer covering of low temperature plasma enhanced chemical vapor deposited silicon dioxide.

公开(公告)号：CA1244149A

公开(公告)日：1988-11-01

申请号：CA503080

申请日：1986-03-03

Applicant: IBM

Inventor： FREEOUF JOHN L ,  JACKSON THOMAS N ,  KIRCHNER PETER D ,  TANG JEFFREY Y-F ,  WOODALL JERRY M

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/68 ,  H01L29/737 ,  H01L29/76 ,  H01L29/06

Abstract: SEMICONDUCTOR BALLISTIC ELECTRON VELOCITY CONTROL STRUCTURE A semiconductor device where an emitter material composition and doping profile produces an electron gas in a base adjacent a hand offset heterojunction interface, the electrons in the electron gas in the base are confined under bias by a low barrier and the ballistic carriers have their kinetic energy controlled to prevent intervalley scattering by an electrostatic barrier that under influence of bias provides an essentially level conduction band in the portion of the base adjacent the collector.