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    Transistor having dielectric stressor elements to apply shearing stress at different depths from semiconductor surface
    2.
    发明专利
    Transistor having dielectric stressor elements to apply shearing stress at different depths from semiconductor surface 有权
    具有电介质压力元件的晶体管适用于半导体表面不同深度的剪切应力

    公开(公告)号：JP2007142429A

    公开(公告)日：2007-06-07

    申请号：JP2006310926

    申请日：2006-11-17

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： CHIDAMBARRAO DURESETI ,  KERN LIM ,  GREENE BRIAN J

    IPC: H01L29/78 ,  H01L21/316 ,  H01L21/8238 ,  H01L27/092

    CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7846

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having dielectric stressor elements and a method for manufacturing the same.
    SOLUTION: There is provided a chip including an active semiconductor region and a field effect transistor (FET) having a channel region, a source region, and a drain region, all of which are arranged in the active semiconductor region. The FET has a lengthwise direction in the direction of the length of the channel region and a transverse direction in the direction of the width of the channel region. An embedded dielectric stressor element has an upper surface extending horizontally at a first depth below the main surface of a part of the active semiconductor region, such as an east edge portion of the active semiconductor region. Surface dielectric stressor elements are arranged adjacent to each other in the transverse direction in the active semiconductor region on the main surface of the active semiconductor region. The surface dielectric stressor element extends from the main surface to a second depth substantially not deeper than the first depth. The stresses applied by the embedded dielectric stressor element and the surface dielectric stressor element collaborate in applying shearing stress to the channel region of the FET.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种具有介电应力元件的半导体器件及其制造方法。 解决方案：提供了包括有源半导体区域的芯片和具有沟道区域，源极区域和漏极区域的场效应晶体管（FET），它们都被布置在有源半导体区域中。 FET在通道区域的长度方向和沟道区域的宽度方向的横向方向上具有长度方向。 嵌入式介电应力元件具有在有源半导体区域的一部分（例如有源半导体区域的东缘部分）的主表面下方的第一深度处水平延伸的上表面。 表面介质应力元件在有源半导体区域的主表面上的有源半导体区域中沿横向彼此相邻布置。 表面介电应力元件从主表面延伸到基本不深于第一深度的第二深度。 嵌入的介电应力元件和表面介电应力元件施加的应力协同作用，对FET的沟道区域施加剪切应力。 版权所有（C）2007，JPO＆INPIT

    Method of manufacturing chip and fet (transistor having dielectric stressor element for applying in-plane shear stress)
    3.
    发明专利
    Method of manufacturing chip and fet (transistor having dielectric stressor element for applying in-plane shear stress) 有权
    制造芯片和FET的方法（具有用于应用平面内应力的电介质应力元件的晶体管）

    公开(公告)号：JP2007123896A

    公开(公告)日：2007-05-17

    申请号：JP2006290967

    申请日：2006-10-26

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： CHIDAMBARRAO DURESETI ,  GREENE BRIAN J ,  KERN LIM

    IPC: H01L29/78

    CPC classification number: H01L29/1083 ,  H01L21/02203 ,  H01L21/02238 ,  H01L21/02258 ,  H01L21/02337 ,  H01L21/31675 ,  H01L29/7833 ,  H01L29/7846

    Abstract: PROBLEM TO BE SOLVED: To provide a transistor having a dielectric stressor for applying in-plane shear stress. SOLUTION: A chip is provided which includes an active semiconductor region and a field effect transistor ("FET") having a channel region, a source region, and a drain region all arranged within the active semiconductor region. The FET has a longitudinal direction in the lengthwise direction of the channel region, and a transverse direction in the widthwise direction of the channel region. A first dielectric stressor element having a horizontally extending upper surface extends below a portion of the active semiconductor region, such as a northwest portion of the active semiconductor region. A second dielectric stressor element having a horizontally extending upper surface extends below one second portion of the active semiconductor region, such as a southeast portion of the active semiconductor region. Each of the first and second dielectric stressor elements shares an edge with the active semiconductor region, and the edges extending in directions away from the upper surface. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种具有用于施加面内剪切应力的介电应力器的晶体管。 解决方案：提供一种芯片，其包括有源半导体区域和具有全部布置在有源半导体区域内的沟道区域，源极区域和漏极区域的场效应晶体管（“FET”）。 FET在沟道区域的长度方向和沟道区域的宽度方向的宽度方向上具有长度方向。 具有水平延伸的上表面的第一介电应激元件在有源半导体区域的一部分的下方延伸，例如有源半导体区域的西北部分。 具有水平延伸的上表面的第二介电应激元件在有源半导体区域的一个第二部分的下方延伸，例如有源半导体区域的东南部分。 第一和第二介电应力元件中的每一个与有源半导体区域共享边缘，并且边缘沿远离上表面的方向延伸。 版权所有（C）2007，JPO＆INPIT

    Method for forming silicon-on-insulator transistor of deep junction
    4.
    发明专利
    Method for forming silicon-on-insulator transistor of deep junction 审中-公开
    形成深度绝缘子晶体管的方法

    公开(公告)号：JP2007294950A

    公开(公告)日：2007-11-08

    申请号：JP2007103478

    申请日：2007-04-11

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： CHIDAMBARRAO DURESETI ,  JOHN JOSEF ELLIS-MONAHAN ,  GREENE BRIAN J

    IPC: H01L21/336 ,  H01L29/786

    CPC classification number: H01L27/1203 ,  H01L21/823814

    Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a transistor device with a dopant depth which is extended and increased so as to have no effect on a channel region of a transistor.
    SOLUTION: The method comprises: (a) a step of providing a substrate comprising a semiconductor-on-insulator structure ("SOI") layer separated from a bulk region in the substrate by an embedded dielectric layer; (b) a step of performing a first implantation to the SOI layer in order to attain a predetermined concentration of dopant in an interface of the SOI layer to the embedded dielectric layer; and (c) a step of performing a second implantation to the SOI layer in order to attain a predetermined concentration of dopant in a polycrystalline semiconductor gate conductor ("poly gate") as well as in a source region and a drain region which are arranged to be adjacent to the poly gate. The maximum depth of the first implantation is deeper than the maximum depth of the second implantation.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于形成具有扩展和增加的掺杂剂深度的晶体管器件的方法，以便对晶体管的沟道区域没有影响。 解决方案：该方法包括：（a）提供包括绝缘体上半导体结构（“SOI”）层的衬底的步骤，该衬底通过嵌入的电介质层与衬底中的本体区域分离; （b）为了在SOI层与嵌入介电层的界面中获得预定浓度的掺杂剂，对SOI层进行第一次注入的步骤; 以及（c）为了在多晶半导体栅极导体（“多晶硅”）以及源极区和漏极区中排列的多个半导体栅极导体（“多晶硅”）以及源极区和漏极区域中的掺杂剂浓度达到预定浓度，对SOI层进行第二注入的步骤 与多门相邻。 第一植入的最大深度比第二植入的最大深度更深。 版权所有（C）2008，JPO＆INPIT

    Transistor having stress-producing dielectric element underlying entire undersurface of active semiconductor region
    5.
    发明专利
    Transistor having stress-producing dielectric element underlying entire undersurface of active semiconductor region 有权
    在有源半导体区域的整个表面下具有应力产生电介质元件的晶体管

    公开(公告)号：JP2007158323A

    公开(公告)日：2007-06-21

    申请号：JP2006311038

    申请日：2006-11-17

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： CHIDAMBARRAO DURESETI ,  KERN RIM ,  GREENE BRIAN J

    IPC: H01L29/786 ,  H01L21/76 ,  H01L29/78

    CPC classification number: H01L29/7849 ,  H01L21/26513 ,  H01L21/31675 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78654

    Abstract: PROBLEM TO BE SOLVED: To provide a transistor having a stress-producing dielectric element which underlies the entire undersurface of an active semiconductor region.
    SOLUTION: A compressive stress is applied to a channel region of a PFET by a structure including an independent stress-producing dielectric element that entirely underlies the bottom surface of an active semiconductor region in which a source, a drain and a channel region of the PFET are disposed. Specifically, the stress-producing dielectric element includes a region of a collapsed oxide which contacts the entire bottom surface of the active semiconductor region so that it has an area of the same spread as an area of the bottom surface. Bird beak-like oxide regions at the edges of the stress-producing dielectric element apply an upward force to the edges of the stress-producing dielectric element to provide a compressive stress to the channel region of the PFET.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种具有产生应力的介电元件的晶体管，其在有源半导体区域的整个下表面的下方。 解决方案：通过包括独立的产生应力的电介质元件的结构将压应力施加到PFET的沟道区域，该电介质元件完全位于有源半导体区域的底表面之下，其中源极，漏极和沟道区域 的PFET。 具体而言，应力产生用电介质元件包括与活性半导体区域的整个底面接触的塌陷氧化物的区域，使得其具有与底面的面积相同的面积。 产生应力的电介质元件边缘处的鸟形喙状氧化物区向产生应力的电介质元件的边缘施加向上的力，以向PFET的沟道区提供压缩应力。 版权所有（C）2007，JPO＆INPIT

    Method of manufacturing chip and fet (transistor having dielectric stressor element)
    6.
    发明专利
    Method of manufacturing chip and fet (transistor having dielectric stressor element) 有权
    制造芯片和FET（具有电介质压力元件的晶体管）的方法

    公开(公告)号：JP2007123898A

    公开(公告)日：2007-05-17

    申请号：JP2006290998

    申请日：2006-10-26

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： CHIDAMBARRAO DURESETI ,  GREENE BRIAN J ,  KERN LIM

    IPC: H01L29/78 ,  H01L21/76

    CPC classification number: H01L21/823481 ,  H01L21/76232 ,  H01L21/823412 ,  H01L29/0653 ,  H01L29/7846

    Abstract: PROBLEM TO BE SOLVED: To provide a structure for adding an effective stress without influencing the arrangement of an element separation region to improve characteristics of a field effect transistor having a channel region, a source region, and a drain region which are arranged in an active semiconductor region. SOLUTION: A buried dielectric stressor element 102 having a horizontally extending upper surface is arranged below one part of an active semiconductor region 104 separated by a trench separation region 106. This dielectric stressor consists of an oxide film by oxidation of a porous silicon, and generates a compression or extension stress based on the degree of porous formation. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于增加有效应力而不影响元件分离区域的布置的结构，以改善具有沟道区域，源极区域和漏极区域的场效应晶体管的特性，所述沟道区域，源极区域和漏极区域布置 在有源半导体区域。 解决方案：具有水平延伸的上表面的埋置介质应力元件102被布置在由沟槽分离区域106分隔开的有源半导体区域104的一部分的下面。该介电应力源由氧化膜由氧化多孔硅 ，并且基于多孔形成的程度产生压缩或延伸应力。 版权所有（C）2007，JPO＆INPIT

    Method for forming germanium-on-insulator semiconductor structure using porous layer and semiconductor structure formed by the method
    7.
    发明专利
    Method for forming germanium-on-insulator semiconductor structure using porous layer and semiconductor structure formed by the method 审中-公开
    使用多孔膜形成的绝缘子半导体结构和半导体结构的方法

    公开(公告)号：JP2007123875A

    公开(公告)日：2007-05-17

    申请号：JP2006284413

    申请日：2006-10-18

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： CHENG KANGGUO ,  GREENE BRIAN J ,  MANDELMAN JACK ALLAN

    IPC: H01L21/02 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12

    CPC classification number: H01L21/76251 ,  H01L21/76245 ,  Y10S438/933

    Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a germanium-on-insulator semiconductor structure using a porous layer, and a semiconductor structure formed by the method.
    SOLUTION: This semiconductor structure comprises a layer containing a single crystal germanium which is preferably substantially pure germanium, a substrate and an embedded insulating layer for separating the layer containing germanium from the substrate. A porous layer which can be converted into a porous silicone layer is formed on the substrate and the layer containing germanium is formed on the porous silicone layer. By converting the porous layer into an oxide layer, an embedded insulating layer can be formed. Alternatively, the layer containing germanium on the porous layer can be moved to an insulating layer on another substrate. After moved, an insulating layer is embedded between the later substrate and the layer containing germanium.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种使用多孔层形成绝缘体上的锗锗的方法，以及通过该方法形成的半导体结构。 解决方案：该半导体结构包括含有优选基本上纯锗的单晶锗的层，用于将含锗层与基板分离的衬底和嵌入绝缘层的层。 在基材上形成能够转化为多孔硅酮层的多孔层，在多孔硅树脂层上形成含锗层。 通过将多孔层转化为氧化物层，可以形成嵌入绝缘层。 或者，可以在多孔层上含有锗的层移动到另一基底上的绝缘层。 移动后，在后面的基板和含有锗的层之间嵌入绝缘层。 版权所有（C）2007，JPO＆INPIT

    THRESHOLD VOLTAGE ADJUSTMENT THROUGH GATE DIELECTRIC STACK MODIFICATION
    9.
    发明专利
    THRESHOLD VOLTAGE ADJUSTMENT THROUGH GATE DIELECTRIC STACK MODIFICATION 未知

    公开(公告)号：CA2750215A1

    公开(公告)日：2010-11-04

    申请号：CA2750215

    申请日：2010-04-22

    Applicant: IBM

    Inventor： GREENE BRIAN J ,  CHUDZIK MICHAEL P ,  HAN SHU-JEN ,  HENSON WILLIAM K ,  LIANG YUE ,  MACIEJEWSKI EDWARD P ,  NA MYUNG-HEE ,  NOWAK EDWARD J ,  YU XIAOJUN

    IPC: H01L21/71 ,  H01L21/77 ,  H01L27/085 ,  H01L27/098

    Abstract: Multiple types of gate stacks (100,..., 600) are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric (30L) is formed on the doped semiconductor well (22, 24). A metal gate layer (42L) is formed in one device area, while the high-k gate dielectric is exposed in other device areas (200, 400, 500, 600). Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer (72L) is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

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