公开(公告)号：EP2415073A4

公开(公告)日：2013-09-11

申请号：EP10759255

申请日：2010-03-29

Applicant: IBM

Inventor： BU HUIMING ,  CHUDZIK MICHAEL P ,  HE WEI ,  JHA RASHMI ,  KIM YOUNG-HEE ,  KRISHNAN SIDDARTH A ,  MO RENEE T ,  MOUMEN NAIM ,  NATZLE WESLEY C

IPC: H01L29/51 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49

CPC classification number: H01L21/28202 ,  H01L21/28176 ,  H01L21/28185 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：WO2008106244A3

公开(公告)日：2010-03-18

申请号：PCT/US2008051067

申请日：2008-01-15

Applicant: IBM ,  CHUDZIK MICHAEL P ,  HE WEI ,  MO RENEE T ,  MOUMEN NAIM ,  NARAYANAN VIJAY ,  PARK DAE-GYU ,  PARUCHURI VAMSI K

Inventor： CHUDZIK MICHAEL P ,  HE WEI ,  MO RENEE T ,  MOUMEN NAIM ,  NARAYANAN VIJAY ,  PARK DAE-GYU ,  PARUCHURI VAMSI K

IPC: H01L21/335

CPC classification number: H01L21/823807 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/78 ,  H01L29/7845

Abstract: A gate structure (200) for complementary metal oxide semiconductor (CMOS) devices includes a first gate stack (116) having a first gate dielectric layer (102) formed over a substrate (100), and a first metal layer (106) formed over the first gate dielectric layer. A second gate stack (118) includes a second gate dielectric layer (102) formed over the substrate and a second metal layer (110) formed over the second gate dielectric layer. The first metal layer is formed in manner so as to impart a tensile stress on the substrate, and the second metal layer is formed in a manner so as to impart a compressive stress on the substrate.

Abstract translation: 用于互补金属氧化物半导体（CMOS）器件的栅极结构（200）包括具有形成在衬底（100）上的第一栅极电介质层（102）的第一栅极堆叠（116）和形成在衬底 第一栅介质层。 第二栅极堆叠（118）包括形成在衬底上的第二栅极电介质层（102）和形成在第二栅极电介质层上的第二金属层（110）。 第一金属层形成为在基板上施加拉伸应力，并且第二金属层以使得在基板上施加压应力的方式形成。

公开(公告)号：SG174129A1

公开(公告)日：2011-10-28

申请号：SG2011057288

申请日：2010-03-29

Applicant: IBM

Inventor： BU HUIMING ,  CHUDZIK MICHAEL P ,  HE WEI ,  JHA RASHMI ,  KIM YOUNG-HEE ,  KRISHNAN SIDDARTH A ,  MO RENEE T ,  MOUMEN NAIM ,  NATZLE WESLEY C

Abstract: A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.

公开(公告)号：MX2011008338A

公开(公告)日：2011-09-01

申请号：MX2011008338

申请日：2010-03-29

Applicant: IBM

Inventor： BU HUIMING ,  CHUDZIK MICHAEL P ,  HE WEI ,  JHA RASHMI ,  KIM YOUNG-HEE ,  KRISHNAN SIDDARTH A ,  MO RENEE T ,  MOUMEN NAIM ,  NATZLE WESLEY C

IPC: H01L21/336

Abstract: El método para formar un dispositivo incluye proporcionar un sustrato, formar una capa interfacial sobre el sustrato, depositar una capa dieléctrica de k alta sobre la capa interfacial, depositar una capa depuradora de oxígeno sobre la capa dieléctrica de k alta y efectuar un recocido. Un transistor de compuerta de metal de k alta incluye un sustrato, una capa interfacial sobre el sustrato, una capa dieléctrica de k alta sobre la capa interfacial y una capa depuradora de oxígeno sobre la capa dieléctrica de k alta.

公开(公告)号：CA2750282A1

公开(公告)日：2010-10-07

申请号：CA2750282

申请日：2010-03-29

Applicant: IBM

Inventor： BU HUIMING ,  CHUDZIK MICHAEL P ,  HE WEI ,  JHA RASHMI ,  KIM YOUNG-HEE ,  KRISHNAN SIDDARTH A ,  MO RENEE T ,  MOUMEN NAIM ,  NATZLE WESLEY C

IPC: H01L21/283 ,  H01L21/285 ,  H01L21/324 ,  H01L29/40 ,  H01L29/43

Abstract: A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.