公开(公告)号：EP2415073A4

公开(公告)日：2013-09-11

申请号：EP10759255

申请日：2010-03-29

Applicant: IBM

Inventor： BU HUIMING ,  CHUDZIK MICHAEL P ,  HE WEI ,  JHA RASHMI ,  KIM YOUNG-HEE ,  KRISHNAN SIDDARTH A ,  MO RENEE T ,  MOUMEN NAIM ,  NATZLE WESLEY C

IPC: H01L29/51 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49

CPC classification number: H01L21/28202 ,  H01L21/28176 ,  H01L21/28185 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1872407A4

公开(公告)日：2011-09-14

申请号：EP06750529

申请日：2006-04-18

Applicant: IBM

Inventor： CARTIER EDUARD A ,  COPEL MATTHEW W ,  DORIS BRUCE B ,  JAMMY RAJARAO ,  KIM YOUNG-HEE ,  LINDER BARRY P ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WONG KEITH KWONG HON

IPC: H01L21/84 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823842

公开(公告)号：WO2006115894A2

公开(公告)日：2006-11-02

申请号：PCT/US2006014516

申请日：2006-04-18

Applicant: IBM ,  CARTIER EDUARD A ,  COPEL MATTHEW W ,  DORIS BRUCE B ,  JAMMY RAJARAO ,  KIM YOUNG-HEE ,  LINDER BARRY P ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WONG KEITH KWONG HON

Inventor： CARTIER EDUARD A ,  COPEL MATTHEW W ,  DORIS BRUCE B ,  JAMMY RAJARAO ,  KIM YOUNG-HEE ,  LINDER BARRY P ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WONG KEITH KWONG HON

IPC: H01L29/76

CPC classification number: H01L21/823842

Abstract: The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.

Abstract translation: 本发明涉及包括位于半导体衬底的一个区域上的至少一个nMOS器件的CMOS结构; 以及位于半导体衬底的另一区域上的至少一个pMOS器件。 根据本发明，所述至少一个nMOS器件包括栅极堆叠，其包括栅极电介质，功函数小于4.2eV的低功函数元素金属，原位金属覆盖层和多晶硅封装层，以及 所述至少一个pMOS包括包括栅极电介质的栅极堆叠，具有大于4.9eV的功函数的高功函数元素金属，金属覆盖层和多晶硅封装层。 本发明还提供了制造这种CMOS结构的方法。

公开(公告)号：JP2007184584A

公开(公告)日：2007-07-19

申请号：JP2006343832

申请日：2006-12-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN TZE-CHIANG ,  DORIS BRUCE B ,  VAMSI K PARUCHURI ,  MICHAEL PATRIK CHUDZIK ,  VIJAY NARAYANAN ,  MICHELLE L STEEN ,  ALESSANDRO CALLEGARI ,  KIM YOUNG-HEE ,  ZHANG YING

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/336 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L21/823857 ,  H01L21/28044 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4925 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: PROBLEM TO BE SOLVED: To prevent the depletion of the gate polysilicon of a CMOS by a gate electrode structure composed of a metal dielectric stack containing a large volume of potassium. SOLUTION: A semiconductor structure is provided by including an n-FET device and a p-FET device. At least either of the devices includes a gate electrode stack having a thin film of a silicon-containing electrode, i.e., polysilicon electrode and a first metal on the silicon-containing electrode. The other of the devices includes a gate electrode stack not having a thin film of a silicon-containing electrode but at least having a first metal gate. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：通过由含有大量钾的金属电介质堆叠构成的栅电极结构来防止CMOS的栅极多晶硅的耗尽。 解决方案：通过包括n-FET器件和p-FET器件来提供半导体结构。 所述器件中的至少一个包括具有含硅电极的薄膜的栅电极堆叠，即多晶硅电极和含硅电极上的第一金属。 另一个器件包括不具有含硅电极薄膜但至少具有第一金属栅极的栅极电极堆叠。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：CA2750282A1

公开(公告)日：2010-10-07

申请号：CA2750282

申请日：2010-03-29

Applicant: IBM

Inventor： BU HUIMING ,  CHUDZIK MICHAEL P ,  HE WEI ,  JHA RASHMI ,  KIM YOUNG-HEE ,  KRISHNAN SIDDARTH A ,  MO RENEE T ,  MOUMEN NAIM ,  NATZLE WESLEY C

IPC: H01L21/283 ,  H01L21/285 ,  H01L21/324 ,  H01L29/40 ,  H01L29/43

Abstract: A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.

公开(公告)号：DE102012217336B4

公开(公告)日：2014-02-13

申请号：DE102012217336

申请日：2012-09-25

Applicant: IBM

Inventor： CHAN KEVIN K ,  D EMIC CHRISTOPHER ,  KIM YOUNG-HEE ,  PARK DAE-GYU ,  YAU JENG-BANG

IPC: H01L21/283 ,  H01L21/336 ,  H01L21/76 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/49

Abstract: Verfahren (100) zum Ersetzen von Halbleitermaterial durch Metall, wobei das Verfahren (100) Folgendes aufweist: Bilden einer strukturierten Halbleiterschicht (126) auf einer Dielektrikumsschicht (124); Bilden (106) einer Feld-Dielektrikumsschicht (144; 134, 136, 138) welche den Raum zwischen Formen auf der strukturierten Halbleiterschicht (126) füllt; Aufbringen (110) von Metall (170) auf die Formen (142); und Tempern (112) des Wafers (120), wobei das aufgebrachte Metall (170) in jeder der Formen (142) den Halbleiter ersetzt, wobei es sich bei den Formen um Silicium-Platzhalter und bei dem Metall (170) um Aluminium handelt, und wobei das Aufbringen (110) von Aluminium (170) das Strukturieren einer aufgebrachten Aluminiumschicht (170) in einem Aluminium-Abhebeverfahren aufweist; und das Tempern (112) des Wafers (120) ein Kurzzeittempern für zwei Stunden bei vierhundert Grad Celsius umfasst.

公开(公告)号：DE102012217336A1

公开(公告)日：2013-06-27

申请号：DE102012217336

申请日：2012-09-25

Applicant: IBM

Inventor： CHAN KEVIN K ,  D EMIC CHRISTOPHER ,  KIM YOUNG-HEE ,  PARK DAE-GYU ,  YAU JENG-BANG

IPC: H01L21/283 ,  H01L21/336 ,  H01L21/76 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/49

Abstract: Ein Verfahren zum Ersetzen von Halbleitermaterial durch Metall, Ersatzmetall-Gate-Feldeffekttransistoren (RMGFETs) und Ersatzmetallkontakte (RMCs) und Chips mit integrierten Schaltungen (ICs), welche die FETs und/oder RMCs umfassen. Eine strukturierte Halbleiterschicht, z.B. Silicium, wird auf einer Dielektrikumsschicht, z.B. eines geschichteten Gate-Dielektrikums, gebildet. Eine Feld-Dielektrikumsschicht füllt den Raum zwischen Formen in der strukturierten Halbleiterschicht. Auf die Formen wird Metall aufgebracht. Der Wafer wird getempert, um Halbleiter in jeder Form durch Metall zu ersetzen, um Metall-FET-Gate-Zonen oder Metallkontakte zu bilden.

公开(公告)号：SG174129A1

公开(公告)日：2011-10-28

申请号：SG2011057288

申请日：2010-03-29

Applicant: IBM

Inventor： BU HUIMING ,  CHUDZIK MICHAEL P ,  HE WEI ,  JHA RASHMI ,  KIM YOUNG-HEE ,  KRISHNAN SIDDARTH A ,  MO RENEE T ,  MOUMEN NAIM ,  NATZLE WESLEY C

Abstract: A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.

公开(公告)号：MX2011008338A

公开(公告)日：2011-09-01

申请号：MX2011008338

申请日：2010-03-29

Applicant: IBM

Inventor： BU HUIMING ,  CHUDZIK MICHAEL P ,  HE WEI ,  JHA RASHMI ,  KIM YOUNG-HEE ,  KRISHNAN SIDDARTH A ,  MO RENEE T ,  MOUMEN NAIM ,  NATZLE WESLEY C

IPC: H01L21/336

Abstract: El método para formar un dispositivo incluye proporcionar un sustrato, formar una capa interfacial sobre el sustrato, depositar una capa dieléctrica de k alta sobre la capa interfacial, depositar una capa depuradora de oxígeno sobre la capa dieléctrica de k alta y efectuar un recocido. Un transistor de compuerta de metal de k alta incluye un sustrato, una capa interfacial sobre el sustrato, una capa dieléctrica de k alta sobre la capa interfacial y una capa depuradora de oxígeno sobre la capa dieléctrica de k alta.