公开(公告)号：EP2415073A4

公开(公告)日：2013-09-11

申请号：EP10759255

申请日：2010-03-29

Applicant: IBM

Inventor： BU HUIMING ,  CHUDZIK MICHAEL P ,  HE WEI ,  JHA RASHMI ,  KIM YOUNG-HEE ,  KRISHNAN SIDDARTH A ,  MO RENEE T ,  MOUMEN NAIM ,  NATZLE WESLEY C

IPC: H01L29/51 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49

CPC classification number: H01L21/28202 ,  H01L21/28176 ,  H01L21/28185 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：JP2007081361A

公开(公告)日：2007-03-29

申请号：JP2006001706

申请日：2006-01-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHAKRAVARTI ASHIMA B ,  CHOU ANTHONY I ,  FURUKAWA TOSHIHARU ,  STEVEN J HOLMES ,  NATZLE WESLEY C

IPC: H01L21/205 ,  H01L21/3065 ,  H01L29/78

CPC classification number: H01L29/7833 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/10126 ,  H01L2224/13023 ,  H01L2924/1305 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for selectively accumulating a germanium spacer on a nitride. SOLUTION: In a method for selectively forming a germanium structure in a semiconductor manufacturing process, a native oxide is removed in a chemical oxide removing (COR) process, then surfaces of heated nitride and oxide are exposed to a germanium-containing gas to selectively form the germanium only on the surface of the nitride, not on the surface of the oxide. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在氮化物上选择性地积聚锗间隔物的结构和方法。 解决方案：在半导体制造工艺中选择性地形成锗结构的方法中，在化学氧化物去除（COR）工艺中除去天然氧化物，然后将加热的氮化物和氧化物的表面暴露于含锗气体 以仅选择性地在氮化物的表面上形成锗，而不是在氧化物的表面上形成锗。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004193575A

公开(公告)日：2004-07-08

申请号：JP2003380487

申请日：2003-11-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NATZLE WESLEY C ,  AHLGREN DAVID C ,  BARBEE STEVEN G ,  CANTELL MARC W ,  JAGANNATHAN BASANTH ,  LANZEROTTI LOUIS D ,  SUBBANNA SESHARDI ,  RYAN W WOOTHRICH

IPC: H01L21/302 ,  H01L21/311 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/732

CPC classification number: H01L29/66242 ,  H01L21/31116 ,  H01L21/8249

Abstract: PROBLEM TO BE SOLVED: To provide an oxide etching process that can be used for manufacturing the emitter and base in a bipolar SiGe device. SOLUTION: The low-temperature process used gives electric insulation between the emitters and bases by COR (chemical oxide removal) etching protecting the insulating TEOS (tetraethylorthosilicate) glass 22. The insulating TEOS glass 22 brings about the capacitance reduction, and promotes to achieve high-speed. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2003017710A

公开(公告)日：2003-01-17

申请号：JP2002149900

申请日：2002-05-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： HUSSEIN I HANAPHY ,  BROWN JEFFREY J ,  NATZLE WESLEY C

IPC: H01L21/336 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795

Abstract: PROBLEM TO BE SOLVED: To provide a technique for forming a double gate/double channel MOSFET structure which has excellent short channel characteristics and a channel length of below 0.05 μm, and to provide the double gate/double channel MOSFET structure itself.
SOLUTION: This technique for manufacturing a MOSFET device which has a double gate/double channel structure uses a damascene process. A gate is located at each side of a silicon film which is about 80 nm or below in vertical thickness and positioned in a gate region. The silicon film functions as the vertical channel region of the structure and interconnects a diffusion region adjacent to the gate region. Due to its double channel feature, the current of this device is twice as large as that of a conventional plane MOSFET of the same physical width.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种形成具有优异的短沟道特性和低于0.05μm的沟道长度的双栅/双沟道MOSFET结构的技术，并提供双栅/双沟道MOSFET结构本身。 解决方案：用于制造具有双栅极/双沟道结构的MOSFET器件的技术使用镶嵌工艺。 栅极位于硅膜的每一侧，其垂直厚度为约80nm或更小，并且位于栅极区域中。 硅膜用作结构的垂直沟道区域并且互连一个与栅极区域相邻的扩散区域。 由于其双通道特性，该器件的电流是相同物理宽度的传统平面MOSFET的两倍。

公开(公告)号：CA2104071C

公开(公告)日：1996-12-17

申请号：CA2104071

申请日：1993-08-13

Applicant: IBM

Inventor： JENG SHWU-JEN ,  NATZLE WESLEY C ,  YU CHIENFAN

IPC: C23F4/00 ,  H01L21/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/306

Abstract: New device and method are described for accurate etching and removal of thin layer by controlling the surface residence time, thickness and composition of reactant containing film. Etching of silicon dioxide at low pressure using a quartz crystal microbalance is illustrated. Usefulness of the invention in the manufacture of microelectronic devices is shown.

公开(公告)号：DE69332013T2

公开(公告)日：2003-01-30

申请号：DE69332013

申请日：1993-10-05

Applicant: IBM

Inventor： JENG SHWU-JEN ,  NATZLE WESLEY C ,  YU CHIENFAN

IPC: H01L21/00 ,  H01L21/302 ,  H01L21/3065 ,  C23F4/00 ,  H01L21/311 ,  H01L21/306

Abstract: New device and method are described for accurate etching and removal of thin layer by controlling the surface residence time, thickness and composition of reactant containing film. Etching of silicon dioxide at low pressure using a quartz crystal microbalance is illustrated. Usefulness of the invention in the manufacture of microelectronic devices is shown.

公开(公告)号：SG46459A1

公开(公告)日：1998-02-20

申请号：SG1996004874

申请日：1993-10-05

Applicant: IBM

Inventor： JENG SWU-JEN ,  NATZLE WESLEY C ,  YU CHIENFAN

IPC: H01L21/00 ,  H01L21/302 ,  C23F4/00 ,  H01L21/3065 ,  H01L21/311

Abstract: New device and method are described for accurate etching and removal of thin layer by controlling the surface residence time, thickness and composition of reactant containing film. Etching of silicon dioxide at low pressure using a quartz crystal microbalance is illustrated. Usefulness of the invention in the manufacture of microelectronic devices is shown.

公开(公告)号：CA2750282A1

公开(公告)日：2010-10-07

申请号：CA2750282

申请日：2010-03-29

Applicant: IBM

Inventor： BU HUIMING ,  CHUDZIK MICHAEL P ,  HE WEI ,  JHA RASHMI ,  KIM YOUNG-HEE ,  KRISHNAN SIDDARTH A ,  MO RENEE T ,  MOUMEN NAIM ,  NATZLE WESLEY C

IPC: H01L21/283 ,  H01L21/285 ,  H01L21/324 ,  H01L29/40 ,  H01L29/43

Abstract: A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.

公开(公告)号：DE69332013D1

公开(公告)日：2002-07-18

申请号：DE69332013

申请日：1993-10-05

Applicant: IBM

Inventor： JENG SHWU-JEN ,  NATZLE WESLEY C ,  YU CHIENFAN

IPC: H01L21/00 ,  H01L21/302 ,  H01L21/3065 ,  C23F4/00 ,  H01L21/311 ,  H01L21/306

Abstract: New device and method are described for accurate etching and removal of thin layer by controlling the surface residence time, thickness and composition of reactant containing film. Etching of silicon dioxide at low pressure using a quartz crystal microbalance is illustrated. Usefulness of the invention in the manufacture of microelectronic devices is shown.

公开(公告)号：CA2104071A1

公开(公告)日：1994-05-10

申请号：CA2104071

申请日：1993-08-13

Applicant: IBM

Inventor： JENG SHWU-JEN ,  NATZLE WESLEY C ,  YU CHIENFAN

IPC: C23F4/00 ,  H01L21/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/306

Abstract: New device and method are described for accurate etching and removal of thin layer by controlling the surface residence time, thickness and composition of reactant containing film. Etching of silicon dioxide at low pressure using a quartz crystal microbalance is illustrated. Usefulness of the invention in the manufacture of microelectronic devices is shown.