公开(公告)号：KR20100123596A

公开(公告)日：2010-11-24

申请号：KR20100030429

申请日：2010-04-02

Applicant: IBM

Inventor： FAROOQ MUKTA G ,  IYER SUBRAMANIAN S

IPC: H01L21/768 ,  H01L21/28

CPC classification number: H01L24/94 ,  H01L21/76898 ,  H01L21/8221 ,  H01L24/16 ,  H01L24/28 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/80345 ,  H01L2224/80357 ,  H01L2224/80801 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83201 ,  H01L2224/83801 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

Abstract: PURPOSE: A 3D integration structure and method using bonded metal planes are provided to connect metal layers through metal to metal. CONSTITUTION: A second semiconductor structure(20) comprises a semiconductor wafer having devices(23), a BEOL wiring(24), an insulating layer(26), oxide, and a metal layer(28). The second semiconductor structure is similar to that of the first semiconductor structure(10). The first and second semiconductor structure have different functions while a metal layer having holes.

Abstract translation: 目的：提供使用接合金属平面的3D集成结构和方法，以通过金属与金属连接金属层。 构成：第二半导体结构（20）包括具有器件（23），BEOL布线（24），绝缘层（26），氧化物和金属层（28）的半导体晶片。 第二半导体结构与第一半导体结构（10）类似。 第一和第二半导体结构具有不同的功能，而具有孔的金属层。

公开(公告)号：EP2422366A4

公开(公告)日：2014-01-22

申请号：EP10767507

申请日：2010-04-08

Applicant: IBM

Inventor： FAROOQ MUKTA G ,  HANNON ROBERT ,  IYER SUBRAMANIAN S ,  KINSER EMILY R

IPC: H01L21/98 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L21/76898 ,  H01L24/06 ,  H01L24/80 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/80896 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2924/00

Abstract: A method of implementing three-dimensional (3D) integration of multiple integrated circuit (IC) devices includes forming a first insulating layer over a first IC device; forming a second insulating layer over a second IC device; forming a 3D, bonded IC device by aligning and bonding the first insulating layer to the second insulating layer so as to define a bonding interface therebetween, defining a first set of vias within the 3D bonded IC device, the first set of vias landing on conductive pads located within the first IC device, and defining a second set of vias within the 3D bonded IC device, the second set of vias landing on conductive pads located within the second device, such that the second set of vias passes through the bonding interface; and filling the first and second sets of vias with a conductive material.

公开(公告)号：EP2313923A4

公开(公告)日：2013-02-20

申请号：EP09808777

申请日：2009-08-19

Applicant: IBM

Inventor： FAROOQ MUKTA G ,  HANNON ROBERT ,  IYER SUBRAMANIAN S ,  KOESTER STEVEN J ,  PORUSHOTHAMAN SAMPATH ,  YU ROY R

IPC: H01L27/06 ,  H01L27/105

CPC classification number: H01L27/105 ,  H01L24/11 ,  H01L27/0688 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

公开(公告)号：WO2013077929A3

公开(公告)日：2013-08-15

申请号：PCT/US2012055061

申请日：2012-09-13

Applicant: IBM ,  FAINSTEIN DANIEL J ,  CESTERO ALBERTO ,  IYER SUBRAMANIAN S ,  KIRIHATA TOSHIAKI

Inventor： FAINSTEIN DANIEL J ,  CESTERO ALBERTO ,  IYER SUBRAMANIAN S ,  KIRIHATA TOSHIAKI

IPC: G11C29/00 ,  G06F21/00

CPC classification number: G06F21/73 ,  G06F21/44 ,  G06F2221/2103 ,  G09C1/00 ,  H04L9/3278 ,  H04L2209/127

Abstract: A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string 275 that includes 2nd ID bit string 290. A retention pause time controls the number of retention fails, adjusted by a BIST engine 625, wherein the fail numbers 803, 920 satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

Abstract translation: 随机固有芯片ID生成采用保留失败签名。 使用测试设置生成第一和第二ID，第一设置比第二设置更严格，在包括第二ID比特串290的第一ID比特串275中创建更多失败。保留暂停时间控制保留失败次数，调整 由BIST引擎625执行，其中失败编号803,920满足预定的失败目标。 验证确认第一个ID是否包含第二个ID位串，该ID是用于认证的ID。 通过具有中间条件的第三ID来启用认证，使得第一ID包括第三ID位串，并且第三ID包括第二ID位串。 中间条件包括用于消除第一和第二ID边界附近的位不稳定问题的保护带。 中间条件在每次ID读取操作时发生变化，从而导致更安全的识别。

公开(公告)号：WO2012177585A3

公开(公告)日：2013-04-25

申请号：PCT/US2012043052

申请日：2012-06-19

Applicant: IBM ,  ANDRY PAUL S ,  FAROOQ MUKTA G ,  HANNON ROBERT ,  IYER SUBRAMANIAN S ,  KINSER EMILY R ,  TSANG CORNELIA K ,  VOLANT RICHARD P

Inventor： ANDRY PAUL S ,  FAROOQ MUKTA G ,  HANNON ROBERT ,  IYER SUBRAMANIAN S ,  KINSER EMILY R ,  TSANG CORNELIA K ,  VOLANT RICHARD P

IPC: H01L21/28 ,  H01L21/768

CPC classification number: H01L21/76846 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.

Abstract translation: 本公开提供了热机械可靠的铜TSV和在BEOL处理期间形成这种TSV的技术。 TSV构成延伸穿过半导体衬底的环形沟槽。 衬底限定沟槽的内侧壁和外侧壁，该侧壁分隔5至10微米的距离。 包括铜或铜合金的导电路径从所述第一介电层的上表面通过所述衬底在所述沟槽内延伸。 基板厚度可以为60微米或更小。 具有导电连接到导电路径的互连金属化的电介质层直接形成在所述环形沟槽上。

公开(公告)号：IN2203CHN2014A

公开(公告)日：2015-06-12

申请号：IN2203CHN2014

申请日：2014-03-21

Applicant: IBM

Inventor： FAINSTEIN DANIEL J ,  CESTERO ALBERTO ,  IYER SUBRAMANIAN S ,  KIRIHATA TOSHIAKI ,  ROBSON NORMAN W ,  ROSENBLATT SAMI

IPC: G11C29/00 ,  G06F21/00

Abstract: A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd creating more fails in the 1st ID bit string 275 that includes 2nd ID bit string 290. A retention pause time controls the number of retention fails adjusted by a BIST engine 625 wherein the fail numbers 803 920 satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation resulting in a more secure identification.

公开(公告)号：DE102013224104B4

公开(公告)日：2019-02-07

申请号：DE102013224104

申请日：2013-11-26

Applicant: IBM

Inventor： CHELLAPPA SRIVATSAN ,  IYER SUBRAMANIAN S ,  KIRIHATA TOSHIAKI ,  ROSENBLATT SAMI

IPC: G06F21/44 ,  G06F11/00

Abstract: System zum Bereitstellen eines Echtheitsnachweisdienstes eines Chips, wobei das System aufweist:eine Echtheitsnachweiseinheit, die ein Erkennungs-Modul, ein Selbsttest-Modul und eine chipspezifische Komponente aufweist, die für jeden Chip einzigartig ist und sich aus einer Schwankungsbreite bei der Fertigung ergibt, wobei die chipspezifische Komponente einem Chip zugehörig ist und ein chipspezifisches Merkmal aufweist, wobei das chipspezifische Merkmal eine Matrix von Werten aufweist, die chipspezifische Eigenschaften repräsentieren, und es sich bei einer Teilmenge der Matrix von Werten um eine Teilmenge in Form des chipspezifischen Merkmals handelt;wobei das Selbsttest-Modul so konfiguriert ist, dass es das chipspezifische Merkmal abruft und dieses an das Erkennungs-Modul übermittelt;wobei das Erkennungs-Modul ferner so konfiguriert ist, dass es das chipspezifische Merkmal empfängt, unter Verwendung des chipspezifischen Merkmals einen ersten Echtheitsnachweiswert erzeugt und diesen in einem Speicher speichert;wobei das Selbsttest-Modul ferner so konfiguriert ist, dass es unter Verwendung einer Echtheitsnachweisabfrage einen zweiten Echtheitsnachweiswert erzeugt, wobei die Echtheitsnachweisabfrage ferner für jeden Matrixwert innerhalb der Teilmenge in Form des chipspezifischen Merkmals eine Adresse aufweist;wobei das Erkennungs-Modul ferner eine Vergleichsschaltung aufweist, die so konfiguriert ist, dass sie den ersten Echtheitsnachweiswert mit dem zweiten Echtheitsnachweiswert vergleicht; undwobei die Vergleichsschaltung ferner so konfiguriert ist, dass sie auf der Grundlage der Ergebnisse des Vergleichs des ersten Echtheitsnachweiswertes mit dem zweiten Echtheitsnachweiswert einen Echtheitsnachweis-Ausgabewert erzeugt.

公开(公告)号：GB2505576B

公开(公告)日：2016-03-23

申请号：GB201318982

申请日：2012-06-19

Applicant: IBM

Inventor： ANDRY PAUL S ,  FAROOQ MUKTA G ,  HANNON ROBERT ,  IYER SUBRAMANIAN S ,  KINSER EMILY R ,  TSANG CORNELIA K ,  VOLANT RICHARD P

IPC: H01L23/48 ,  H01L21/28 ,  H01L21/768

Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.

公开(公告)号：DE112012004439T5

公开(公告)日：2014-07-17

申请号：DE112012004439

申请日：2012-09-13

Applicant: IBM

Inventor： CESTERO ALBERTO ,  IYER SUBRAMANIAN S ,  ROBSON NORMAN W ,  ROSENBLATT SAMI ,  FAINSTEIN DANIEL J ,  KIRIHATA TOSHIAKI

IPC: G11C29/00 ,  G06F21/00

Abstract: Eine Erzeugung einer zufälligen intrinsischen Chip-ID verwendet eine Speicherfehlersignatur. Eine 1. und eine 2. ID werden unter Verwendung von Testeinstellungen erzeugt, wobei eine 1. Einstellung restriktiver als die 2. ist und in der ersten ID-Bitzeichenkette 275, welche die 2. ID-Bitzeichenkette 290 enthält, mehr Fehler erzeugt werden. Eine Speicherpausenzeit-Steuerung steuert eingestellt durch eine BIST-Engine 625 die Anzahl von Speicherfehlern, wobei die Fehleranzahlen 803, 920 ein vorgegebenes Fehlerziel erfüllen. Eine Überprüfung bestätigt, ob die 1. ID die 2. ID-Bitzeichenkette enthält, wobei es sich bei der ID um die für die Authentifizierung verwendete handelt. Die Authentifizierung wird durch eine 3. ID mit einer derartigen Zwischenbedingung ermöglicht, dass die 1. ID die 3. ID-Bitzeichenkette enthält und die 3. ID die 2. ID-Bitzeichenkette enthält. Die Zwischenbedingung enthält ein Wächterband, um ein Bitinstabilitätsproblem nahe der 1. und 2. ID-Grenze zu beseitigen. Die Zwischenbedingung wird bei jedem ID-Lesevorgang geändert, was zu einer sichereren Identifikation führt.

公开(公告)号：GB2505576A

公开(公告)日：2014-03-05

申请号：GB201318982

申请日：2012-06-19

Applicant: IBM

Inventor： ANDRY PAUL S ,  FAROOQ MUKTA G ,  HANNON ROBERT ,  IYER SUBRAMANIAN S ,  KINSER EMILY R ,  TSANG CORNELIA K ,  VOLANT RICHARD P

IPC: H01L23/48 ,  H01L21/28 ,  H01L21/768

Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.