公开(公告)号：EP2313923A4

公开(公告)日：2013-02-20

申请号：EP09808777

申请日：2009-08-19

Applicant: IBM

Inventor： FAROOQ MUKTA G ,  HANNON ROBERT ,  IYER SUBRAMANIAN S ,  KOESTER STEVEN J ,  PORUSHOTHAMAN SAMPATH ,  YU ROY R

IPC: H01L27/06 ,  H01L27/105

CPC classification number: H01L27/105 ,  H01L24/11 ,  H01L27/0688 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

公开(公告)号：JP2005123580A

公开(公告)日：2005-05-12

申请号：JP2004234182

申请日：2004-08-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHU JACK O ,  KOESTER STEVEN J ,  OUYANG QIQING C

IPC: H01L29/06 ,  H01L21/20 ,  H01L21/335 ,  H01L21/338 ,  H01L29/778 ,  H01L29/78 ,  H01L29/786 ,  H01L29/812

CPC classification number: H01L29/66431 ,  H01L29/7782 ,  Y10S438/933 ,  Y10S438/938

Abstract: PROBLEM TO BE SOLVED: To provide a high-mobility semiconductor layer and a structure of a MODFET (modulation-doped field-effect transistor) which include a high-mobility conduction channel and simultaneously maintain a counter dope to reduce a harmful short channel effect. SOLUTION: A high-performance n-MODFET transistor device is formed by providing an insulating gate dielectric on an Si cap layer, a gate electrode disposed on the insulating gate dielectric, and n-type source and drain contact areas which are disposed in contact with one side of the gate electrode and stretch from a surface of a multilayer structure into a p-type doped portion of a relaxed Si 1-X Ge X layer. This MODFET design includes the high-mobility conduction channel. This method forms a counter doped portion by using a standard technique such as ion implantation and bringing a high-mobility channel close to the counter doped portion without reducing a mobility. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供包括高迁移率传导通道的MODFET（调制掺杂场效应晶体管）的高迁移率半导体层和结构，并且同时保持反向掺杂以减少有害短路 渠道效应。 解决方案：通过在Si覆盖层上提供绝缘栅极电介质，设置在绝缘栅极电介质上的栅极电极和设置在绝缘栅极电介质上的n型源极和漏极接触区域来形成高性能n-MODFET晶体管器件 与栅电极的一侧接触并且从多层结构的表面拉伸成松弛的Si 1-X SB Ge x SB层的p型掺杂部分。 该MODFET设计包括高迁移率传导通道。 该方法通过使用诸如离子注入的标准技术形成反掺杂部分，并使高迁移率通道靠近反掺杂部分而不降低迁移率。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2007149581A3

公开(公告)日：2008-08-28

申请号：PCT/US2007014684

申请日：2007-06-25

Applicant: IBM ,  KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

Inventor： KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

IPC: H01L21/336

CPC classification number: H01L29/7787 ,  H01L29/66462

Abstract: A semiconductor-containing heterostructure including, from bottom to top, a IH-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a HI-V compound semiconductor barrier layer, and an optional, yet preferred, IH-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The HI-V compound semiconductor buffer layer and the HI-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the pi-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

Abstract translation: 一种含半导体的异质结构，包括从底部到顶部的IH-V化合物半导体缓冲层，III-V族化合物半导体沟道层，HI-V族化合物半导体阻挡层和任选的，但优选的IH-V化合物 提供半导体盖层。 阻挡层可以是掺杂的，或者优选地是未掺杂的。 HI-V化合物半导体缓冲层和HI-V化合物半导体阻挡层由具有比p-V化合物半导体沟道层的带隙更宽的带隙的材料构成。 由于宽带隙材料用于缓冲层和阻挡层，并且窄带隙材料用于沟道层，载流子在特定栅极偏置范围内被限制在沟道层上。 本发明的异质结构可以用作场效应晶体管中的掩埋沟道结构。

公开(公告)号：WO2007149581A2

公开(公告)日：2007-12-27

申请号：PCT/US2007014684

申请日：2007-06-25

Applicant: IBM ,  KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

Inventor： KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

IPC: H01L21/336 ,  H01L29/778

CPC classification number: H01L29/7787 ,  H01L29/66462

Abstract: A semiconductor-containing heterostructure including, from bottom to top, a IH-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a HI-V compound semiconductor barrier layer, and an optional, yet preferred, IH-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The HI-V compound semiconductor buffer layer and the HI-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the pi-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

Abstract translation: 含半导体的异质结构包括从下至上的IH-V化合物半导体缓冲层，III-V族化合物半导体沟道层，HI-V族化合物半导体阻挡层和任选的，但优选的IH-V化合物 提供半导体盖层。 阻挡层可以是掺杂的，或者优选地是未掺杂的。 HI-V化合物半导体缓冲层和HI-V化合物半导体阻挡层由具有比p-V化合物半导体沟道层的带隙更宽的带隙的材料构成。 由于宽带隙材料用于缓冲层和阻挡层，并且窄带隙材料用于沟道层，所以载流子在特定栅极偏置范围内被限制在沟道层。 本发明的异质结构可以用作场效应晶体管中的掩埋沟道结构。

公开(公告)号：WO2005083750A3

公开(公告)日：2005-10-27

申请号：PCT/US2005005570

申请日：2005-02-22

Applicant: IBM ,  CHU JACK O ,  DEHLINGER GABRIEL K ,  GRILL ALFRED ,  KOESTER STEVEN J ,  OUYANG QIGING ,  SCHAUB JEREMY D

Inventor： CHU JACK O ,  DEHLINGER GABRIEL K ,  GRILL ALFRED ,  KOESTER STEVEN J ,  OUYANG QIGING ,  SCHAUB JEREMY D

IPC: H01L31/101

CPC classification number: H01L31/101

Abstract: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n-­and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.

Abstract translation: 本发明解决了创建与Si CMOS技术兼容的高速，高效率光电探测器的问题。 该结构由薄SOI衬底上的Ge吸收层组成，并利用隔离区，交替的n型和p型触点以及低电阻表面电极。 该器件利用掩埋绝缘层隔离底层衬底中产生的载流子，通过利用Ge吸收层在广谱上获得高量子效率，利用薄吸收层和窄电极间距实现低电压操作，以及兼容性 凭借其平面结构和使用IV族吸收材料而具有CMOS器件。 用于制造光电检测器的方法使用在薄SOI或外延氧化物上直接生长Ge，并且随后进行热退火以实现高质量的吸收层。 该方法限制了可用于相互扩散的Si的量，由此允许Ge层退火而不会导致Ge层基本上被下面的Si稀释。

公开(公告)号：DE112010005236T5

公开(公告)日：2012-11-15

申请号：DE112010005236

申请日：2010-12-06

Applicant: IBM

Inventor： KOESTER STEVEN J ,  LIU FEI

IPC: H01L21/00 ,  H01L21/98 ,  H01L23/48

Abstract: Eine Halbleiterstruktur umfasst Rückseitenpseudostecker, die in ein Substrat eingebettet sind. Die Rückseitenpseudostecker können eine leitfähige Struktur sein, welche die vertikale Wärmeleitfähigkeit der Halbleiterstruktur verbessert und eine elektrische Entkopplung der Signale in den Durchkontaktierungen durch das Substrat (TSVs) im Substrat bereitstellt. Der Rückseitenpseudostecker kann einen Hohlraum zum Ausgleichen von Volumenänderungen in anderen Komponenten in dem Substrat umfassen, wodurch mechanische Spannungen in dem Substrat während der Temperaturwechsel und während des Betriebs des Halbleiterchips verringert werden. Der Rückseitenpseudostecker, der den Hohlraum umfasst, kann aus einem isolierenden Material oder einem leitfähigen Material bestehen. Die erfinderischen Strukturen können dazu eingesetzt werden, dreidimensionale Strukturen auszubilden, die eine vertikale Chipintegration aufweisen, in welcher die Wärmeleitfähigkeit zwischen den Wafern verbessert wird, das Übersprechen zwischen den durch die TSVs übertragenen Signalen verringert wird und/oder die mechanischen Spannungen auf die TSVs vermindert werden.

公开(公告)号：DE602005001401T2

公开(公告)日：2008-02-21

申请号：DE602005001401

申请日：2005-02-22

Applicant: IBM

Inventor： CHU JACK O ,  DEHLINGER GABRIEL K ,  GRILL ALFRED ,  KOESTER STEVEN J ,  OUYANG QIGING ,  SCHAUB JEREMY D

IPC: H01L31/101

Abstract: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.

公开(公告)号：DE602005001401D1

公开(公告)日：2007-07-26

申请号：DE602005001401

申请日：2005-02-22

Applicant: IBM

Inventor： CHU JACK O ,  DEHLINGER GABRIEL K ,  GRILL ALFRED ,  KOESTER STEVEN J ,  OUYANG QIGING ,  SCHAUB JEREMY D

IPC: H01L31/101

Abstract: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.