公开(公告)号：JP2002198538A

公开(公告)日：2002-07-12

申请号：JP2001319845

申请日：2001-10-17

Applicant: IBM

Inventor： ADKISSON JAMES W ,  AGNELLO PAUL D ,  ARNE W BALLANTINE ,  DIVAKARUNI RAMA ,  JONES ERIN C ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L29/161 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a dual-gate transistor having a relatively thin epitaxial growth channel. SOLUTION: The epitaxial growth channel is formed, and then a damascene gate is formed, thus forming a silicon-on-insulator(SOI) MOSFET of a dual gate. In the dual-gate MOSFET, a narrow channel should be provided, thus increasing a current drive per layout width, and achieving low out conductance.

公开(公告)号：JP2005340816A

公开(公告)日：2005-12-08

申请号：JP2005147746

申请日：2005-05-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHAN KEVIN K ,  MILLER ROBER J ,  JONES ERIN C ,  AJMERA ATUL

IPC: H01L21/225 ,  C30B1/00 ,  H01L21/20 ,  H01L21/205 ,  H01L21/316 ,  H01L21/331 ,  H01L21/336 ,  H01L21/36 ,  H01L21/8222 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/0843 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02507 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/2252 ,  H01L21/31695 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a manufacturing method of a MOSFET device having a polycrystalline SiGe junction.
SOLUTION: Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers produce a SiGe junction. The deposited layers are doped, and then the dopants are outdiffused into the device body. A thin porous oxide layer between the polycrystalline Ge and Si layers enhances the isotropy of the SiGe junction.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供具有多晶SiGe结的MOSFET器件的结构和制造方法。 解决方案：Ge选择性地生长在Si上，而Si选择性地生长在Ge上。 Ge和Si层的交替沉积产生SiGe结。 沉积的层被掺杂，然后掺杂物向外扩散到器件本体中。 多晶Ge和Si层之间的薄多孔氧化物层增强了SiGe结的各向同性。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2004207705A

公开(公告)日：2004-07-22

申请号：JP2003409571

申请日：2003-12-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DOKUMACI OMER H ,  DORIS BRUCE B ,  HEGDE SURYANARAYAN G ,  IEONG MEIKEI ,  JONES ERIN C

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/337 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/80

CPC classification number: H01L29/66916 ,  H01L29/42316 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/802

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a double-gate type field effect transistor (DGFET) of a self-aligning planar type with a front gate and a back gate aligned.
SOLUTION: A method of manufacturing this double-gate type field effect transistor (DGFET) comprises: a process of preparing a stacked double-gate structure provided with at least a back gate 14, a back gate dielectric provided on the back gate 14, a channel layer provided on the back gate dielectric, a front gate dielectric provided on the channel layer, and a front gate 22 provided on the front gate dielectric; a process of patterning the front gate 22 of the stacked double-gate structure; a process of forming a sidewall spacer on the exposed sidewall of the pattered front gate 22; and a process of forming a carrier depletion zone at a part of the back gate and allowing the carrier depletion zone to align the back gate to the front gate.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：DE60138000D1

公开(公告)日：2009-04-30

申请号：DE60138000

申请日：2001-10-15

Applicant: IBM

Inventor： ADKISSON JAMES W ,  AGNELLO PAUL D ,  BALLANTINE ARNE W ,  DIVAKARUNI RAMA ,  JONES ERIN C ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/336 ,  H01L29/161 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

公开(公告)号：AT426246T

公开(公告)日：2009-04-15

申请号：AT01308767

申请日：2001-10-15

Applicant: IBM

Inventor： ADKISSON JAMES W ,  AGNELLO PAUL D ,  BALLANTINE ARNE W ,  DIVAKARUNI RAMA ,  JONES ERIN C ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/336 ,  H01L29/161 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.