公开(公告)号：CA1306299C

公开(公告)日：1992-08-11

申请号：CA600748

申请日：1989-05-25

Applicant: IBM

Inventor： LARKY STEVEN P ,  LUCAS BRUCE D ,  MCCABE DANIEL H ,  RODGERS TODD K

IPC: G09G5/00 ,  G06T5/00 ,  G09G3/20 ,  G09G5/02 ,  G09G5/06 ,  H04N1/41 ,  H04N1/64 ,  G09G1/28

Abstract: YO988-030 A color display device which includes dither apparatus for each primary color to be displayed. A dither matrix provides a dither signal output as a function of the position of a pixel on the color display device. An input primary color signal includes an integer signal and a fraction signal. The integer signal is incremented by an incrementer. There is means for providing an output primary color signal which is the incremented signal whenever a predetermined relationship exists between the dither signal and the fraction signal, and which is the integer signal whenever the predetermined relationship does not exist.

公开(公告)号：CA1313415C

公开(公告)日：1993-02-02

申请号：CA589106

申请日：1989-01-25

Applicant: IBM

Inventor： GUPTA SATISH ,  LARKY STEVEN P ,  PEEVERS ALAN W ,  ST CLAIR JOE C

IPC: G09G1/02 ,  G06F3/153 ,  G06F12/08 ,  G06F12/10 ,  G09G5/00 ,  G09G5/14 ,  G09G5/36 ,  G09G5/39 ,  G09G1/16

Abstract: Y0988-006 A display control means such as a virtual display adapter allows the advanced functions of a display controller to be utilized in a large area of memory in addition to the normal use in display memory. This large area of memory includes system memory, and efficient access to this large area of memory is permitted for normal system use. The display controller also functions with non-contiguous and non-resident bitmaps. The flexibility of demand-paged virtual memory is utilized for display tasks, as display bitmaps may be written to the large area of memory as well as the display memory.

公开(公告)号：CA2051176A1

公开(公告)日：1992-04-13

申请号：CA2051176

申请日：1991-09-11

Applicant: IBM

Inventor： BRASE DEBORAH D ,  LARKY STEVEN P ,  ST CLAIR JOE C ,  SIDOLI PAOLO

IPC: G06F3/153 ,  G06F3/033 ,  G06F3/048 ,  G06T1/60 ,  G06T11/80 ,  G06T15/30 ,  G09G5/36 ,  G06T15/00 ,  G06T15/20

Abstract: AT9-90-002 APPARATUS AND METHOD FOR RELATING A POINT OF SELECTION TO AN OBJECT IN A GRAPHICS DISPLAY SYSTEM Apparatus and methods for picking three dimensional objects from images depicted on a video display. The displayed objects are selectively rerendered. During such rerendering the object pixels are compared in depth to the data in a Z buffer for determining visibility. The number and size of the objects subject to rerendering by the rasterization processor is constrained by using the front end graphics processor to define object extents and by rerendering only extents which have been clipped to the boundaries of the pick window. The rerendering operation does not alter the three dimensional graphics image stored in and repetitively scanned from the frame buffer. Selection between multiple objects within the pick window can include a weighted comparison using a pick plane memory to store visibility data by object.

公开(公告)号：CA2055785A1

公开(公告)日：1992-05-16

申请号：CA2055785

申请日：1991-10-22

Applicant: IBM

Inventor： JOHNSON LEE E JR ,  KOKOSZKA DARYL J ,  LARKY STEVEN P ,  SIDOLI PAOLO

IPC: G06F3/153 ,  G06T11/20 ,  G06T15/83 ,  G06T15/87

Abstract: AT9-89-107 A graphics processor including an interface for providing triangle primitives and line primitives representing a graphical image, a line drawer for receiving line primitives and for rendering the line primitives, and a triangle interpolator for receiving the triangle primitives from the interface and for providing line primitives therefrom to the line drawer, wherein the interface includes a register for storing graphics image line primitives and for selectively providing the stored line primitives to the line drawer.

公开(公告)号：CA2053947A1

公开(公告)日：1992-05-16

申请号：CA2053947

申请日：1991-10-22

Applicant: IBM

Inventor： JOHNSON LEE E JR ,  KOKOSZKA DARYL J ,  LARKY STEVEN P ,  SIDOLI PAOLO

IPC: G06F3/153 ,  G06T11/20 ,  G06T15/00 ,  G06T15/80 ,  G06F15/66

Abstract: r9-90-022 A graphics processor including an interface for providing triangle primitives representing a graphics image, a triangle interpolator coupled to the interface for interpolating a triangle primitive and serially computing multiple line primitives from the triangle primitive, a line renderer coupled to the triangle interpolator for receiving a line primitive from the triangle interpolator and for providing pixels representing the line primitive while the triangle interpolator is computing another line primitive.

公开(公告)号：CA1309199C

公开(公告)日：1992-10-20

申请号：CA579392

申请日：1988-10-05

Applicant: IBM

Inventor： BUTLER NICHOLAS D ,  HOMEWOOD BRIAN C ,  LARKY STEVEN P

IPC: G06F3/153 ,  G06T9/00 ,  G09G1/00 ,  G09G1/02 ,  G09G5/00 ,  G09G5/36 ,  G09G5/39 ,  G09G5/395 ,  G09G1/16

Abstract: BIT GATING FOR EFFICIENT USE OR RAMS IN VARIABLE PLANE DISPLAYS Apparatus for serializing 2M parallel outputs of an all points addressable memory into successive data groups, each data group corresponding to a respective value for a pixel in an image wherein the bit-length of the pixel value is selectable, the apparatus comprising: a gate circuit having (i) 2M parallel input junctions connected to the outputs of the memory and (ii) 2N output junctions, wherein the gate circuit selectively converts each set of 2M parallel inouts at said input junctions into 2M-n successive data groups, each group having a bit-length of 2n bits, wherein each group is transmitted to 2n of the 2N out put junctions; and a communication element for conveying to the gate circuit a signal which controls the bit-length 2n of data groups, wherein n is an integer 1 ? n ? N ? M.

公开(公告)号：CA2055784C

公开(公告)日：1998-05-19

申请号：CA2055784

申请日：1991-10-22

Applicant: IBM

Inventor： KOKOSZKA DARYL J ,  LARKY STEVEN P ,  JOHNSON LEE E JR

IPC: G06F12/08 ,  G06T15/00

Abstract: A memory apparatus including a circuit for receiving and serially storing a plurality of instructions and a plurality of buffer memories each including a buffer controller for regulating access to that buffer. Also included is a circuit, connected to each buffer controller and said receiving circuit, for accessing one or more of said buffers in response to at least one other serially stored instruction, accessing at least one remaining buffer.

公开(公告)号：CA2055784A1

公开(公告)日：1992-05-16

申请号：CA2055784

申请日：1991-10-22

Applicant: IBM

Inventor： JOHNSON LEE E JR ,  KOKOSZKA DARYL J ,  LARKY STEVEN P

IPC: G06F12/08 ,  G06T15/00

Abstract: A memory system including a circuit for receiving and serially storing a plurality of instructions and a plurality of buffer memories each including a buffer controller 800, 820 for regulating access to that buffer. Also included is a circuit 830, connected to each buffer controller and said receiving circuit, for accessing one or more of said buffers in response to a first serially stored instruction while, in response to at least one other serially stored instruction, accessing at least one remaining buffer.