-
公开(公告)号：DE3381072D1
公开(公告)日：1990-02-08
申请号：DE3381072
申请日：1983-08-31
Applicant: IBM
Inventor： LEININGER JOEL CALVIN
IPC: H03K3/286 , H03K3/2885 , H03K19/086 , H03K3/288 , H03K19/173 , H03K19/003
Abstract: The set/reset latch circuit comprises a multi-level differential cascode current switch (DCCS) tree (11) operable to develop set and reset control pulses in response to logic input signals, a constant current source (10) two load resistors (14-L, 14-R), a bistable device (12) comprising a cross-coupled pairs of transistors and switching from a first state to a second state in response to respectively to the set and reset control pulses. The DCCS tree (11) includes means (16) for connecting the current source (10) to the bistable device (12) selectively through one of two different serial current paths of the tree (11) to provide a current to one of the load resistors (14-L, 14-R) through one of the cross coupled pair of transistors to hold the bistable device in one state in the absence of the set and reset control pulses.
-
公开(公告)号：IT1148827B
公开(公告)日：1986-12-03
申请号：IT2199280
申请日：1980-05-13
Applicant: IBM
Inventor： BLISS FLOYD RUSSELL , FAIRCHILD PETER TAPPEN , LEININGER JOEL CALVIN
-
公开(公告)号：DE3379917D1
公开(公告)日：1989-06-29
申请号：DE3379917
申请日：1983-02-01
Applicant: IBM
Inventor： LEININGER JOEL CALVIN , MOORE VICTOR STEWART , STAHL WILLIAM L
Abstract: A microword control mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed data processor. This microword control mechanism includes circuitry (15, 20) responsive to a processor instruction to be executed for providing an instruction dependent signal uniquely representative of such instruction. This microword control mechanism also includes sequence counter circuitry (18) for supplying a sequence of -number signals. This microword control mechanism further includes a programmable logic array (17) responsive to the instruction dependent signal and to the sequence of number signals for producing a sequence of microwords needed to execute the processor instruction.
-
公开(公告)号：DE2962433D1
公开(公告)日：1982-05-19
申请号：DE2962433
申请日：1979-06-01
Applicant: IBM
Inventor： FAIRCHILD PETER TAPPEN , LEININGER JOEL CALVIN
IPC: G06F9/22 , G06F9/30 , G06F9/305 , G06F9/318 , G06F9/34 , G06F9/355 , G06F12/06 , G06F13/00 , G06F9/06
Abstract: A programmable control latch mechanism which is particularly useful in a microprocessor. One or more control latches are provided which can be set or reset under direct program control directly from the instruction register of a data processor by the loading therein of a unique program instruction. The unique instruction includes for each control latch two predetermined bit positions, one of which determines whether or not the control latch is to be changed and the other of which determines the binary value to which the control latch is to be changed. This enables anywhere from one to all of the control latches to be changed by a single instruction and enables each latch which is changed to be changed to any desired binary value. The control latch outputs can be used for storage page selection, direct control of external devices or circuits, selection of internal processor functions and the like.
-
公开(公告)号：IT8021992D0
公开(公告)日：1980-05-13
申请号：IT2199280
申请日：1980-05-13
Applicant: IBM
Inventor： BLISS FLOYD RUSSELL , FAIRCHILD PETER TAPPEN , LEININGER JOEL CALVIN
-
Patent Agency Ranking
公开(公告)号：AU4679379A
公开(公告)日：1980-01-03
申请号：AU4679379
申请日：1979-05-08
Applicant: IBM
Inventor： FAIRCHILD PETER TAPPEN , LEININGER JOEL CALVIN
Abstract: A programmable control latch mechanism which is particularly useful in a microprocessor. One or more control latches are provided which can be set or reset under direct program control directly from the instruction register of a data processor by the loading therein of a unique program instruction. The unique instruction includes for each control latch two predetermined bit positions, one of which determines whether or not the control latch is to be changed and the other of which determines the binary value to which the control latch is to be changed. This enables anywhere from one to all of the control latches to be changed by a single instruction and enables each latch which is changed to be changed to any desired binary value. The control latch outputs can be used for storage page selection, direct control of external devices or circuits, selection of internal processor functions and the like.
-
公开(公告)号：DE2814078A1
公开(公告)日：1978-11-09
申请号：DE2814078
申请日：1978-04-01
Applicant: IBM
Inventor： LEININGER JOEL CALVIN , TAYLOR GEORGE PHILLIPS
Abstract: This carry save adder (CSA) utilizes a pair of edge-triggered flip-flops as output manifesting elements at each CSA bit position, one of these flip-flops being the "sum trigger" which registers the half-sum value (herein called the "sum bit"), and the other flip-flop of the pair being the "carry trigger" which registers the carry value resulting from the binary addition performed by the CSA at that bit position. Each trigger has a latch portion for storing a sum or carry bit value that can be set or changed only at the leading edge of a clock pulse, being stable in the period between clock pulses. A latched sum or carry output bit value at any CSA bit position can be re-entered at any time as input to the same bit position or another CSA bit position, depending upon the operation to be performed (add, left or right shift, or complement). Each trigger also produces an unlatched output sum or carry value known as a "presum" or "precarry" bit. These unlatched bit values may be utilized for trial or test purposes, such as inputs to a lookahead logic network for determining whether a proposed complemental subtraction in a division operation can or cannot be successfully performed.
-
公开(公告)号：DE3368771D1
公开(公告)日：1987-02-05
申请号：DE3368771
申请日：1983-08-31
Applicant: IBM
Inventor： DAVIS JAMES WILLIAM , LEININGER JOEL CALVIN , MUNOZ-BUSTAMANTE CARLOS , ROBBINS GORDON JAY
IPC: G01R31/28 , G01R31/3185 , H01L21/822 , H01L27/04 , H03K3/286 , H03K3/2885 , H03K3/288
-
公开(公告)号：DE3069401D1
公开(公告)日：1984-11-15
申请号：DE3069401
申请日：1980-04-25
Applicant: IBM
Inventor： BLISS FLOYD , FAIRCHILD PETER TAPPEN , LEININGER JOEL CALVIN
-
公开(公告)号：AU3392778A
公开(公告)日：1979-09-13
申请号：AU3392778
申请日：1978-03-07
Applicant: IBM
IPC: G06F13/12 , G06F7/00 , G06F9/38 , G06F13/38 , G06F15/16 , G06F15/17 , G06F15/177 , G06F3/00 , G06F9/16
Abstract: An interface comprising normal asynchronous I/O interface hardware in combination with certain additional synchronizing connections is provided between a microcoded central processing unit (CPU) and a microcoded secondary processor (such as a floating point processor) for enabling these processors to function conjointly under common timing control as though they were natively attached to each other insofar as the execution of their respective microcodes is concerned. The secondary processor shares the normal I/O interface with the I/O devices for data transfer purposes in such fashion that data can be transferred between any of the I/O devices and the CPU in cycle steal mode when the secondary processor is internally occupied with executing an operation delegated to it by the central processor, and when the secondary processor is ready to store data which it has produced, I/O data transfers in cycle steal mode can be made concurrently with data transfers between the secondary processor and the CPU on a demand multiplex basis. Coordinating signals are passed between the processors at certain steps during the execution of their respective microcodes to maintain these microcodes in proper timed relationship with each other.
-
-
-
-
-
-
-
-
-
Search Results
16
records
(took 0.047 seconds)
