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    2.
    发明专利
    未知

    公开(公告)号：DE3783672T2

    公开(公告)日：1993-07-08

    申请号：DE3783672

    申请日：1987-05-12

    Applicant: IBM

    Inventor： BHATIA HARSARAN SINGH ,  JONES HARRY JORDAN ,  MALAVIYA SHASHI DHAR

    IPC: H03K19/082 ,  H03K19/086 ,  H03K19/173 ,  H02H3/38 ,  G05F1/20

    Abstract: A new dotting circuit for integrated circuit chips which provides line switching, as well as simultaneous true and complementary outputs (46,48), while eliminating the need for the standard collector circuit voltage clamp. This circuit is implemented by the collector dotting of two or more input transistors (12,22), the collector dotting of their respective reference transistors (55,56), the emitter dotting of one input transistor (12) and a reference transistor (55) to a constant current source (90), the emitter dotting of the other input transistor (22) and the other reference transistor (56) to a different constant current source (100), and an inhibit circuit (72) for permitting current to flow to only one of the emitter-dotted circuits in accordance with a logic control signal.

    TWO STATE MEMORY CELL
    3.
    发明专利
    TWO STATE MEMORY CELL 未知

    公开(公告)号：DE3279944D1

    公开(公告)日：1989-10-19

    申请号：DE3279944

    申请日：1982-06-02

    Applicant: IBM

    Inventor： MALAVIYA SHASHI DHAR

    IPC: G11C11/41 ,  G11C11/38

    Abstract: A two state memory cell includes a bipolar transistor (11) and a tunnel diode (16) shunted across the base-collector junction thereof. A constant operating current is established through the transistor (11) and the tunnel diode (16). The voltage across the tunnel diode (16) may thus be maintained at one of two stable levels, while the bipolar transistor (11) is kept on regardless of the tunnel diode voltage, which determines the ZERO or ONE state of the cell.Since the transistor (11) is not switched on and off when the memory state (corresponding to the two tunnel diode voltage levels) changes, memory cell switching speed is not degraded by transistor switching delay. Moreover, since the current in the tunnel diode (16) is maintained constant, preferably at a value midway between the tunnel diode peak and valley currents, the noise margin of the memory cell is enhanced and the possibility of false switching reduced. The tunnel diode/bipolar transistor combination may be formed on a semiconductor substrate as an integrated structure, thereby providing a high density memory cell.

    METHOD FOR FORMING INTEGRATED CIRCUITS HAVING A PATTERN OF NARROW DIMENSIONED DIELECTRIC REGIONS
    4.
    发明专利
    METHOD FOR FORMING INTEGRATED CIRCUITS HAVING A PATTERN OF NARROW DIMENSIONED DIELECTRIC REGIONS 未知

    公开(公告)号：DE3177099D1

    公开(公告)日：1989-10-05

    申请号：DE3177099

    申请日：1981-06-23

    Applicant: IBM

    Inventor： GOTH GEORGE RICHARD ,  MAGDO INGRID EMESE ,  MALAVIYA SHASHI DHAR

    IPC: H01L21/3205 ,  H01L21/033 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/331 ,  H01L21/336 ,  H01L21/60 ,  H01L29/41 ,  H01L29/417 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78 ,  H01L21/00 ,  H01L21/31

    Abstract: A method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions and, more particularly self-aligned metal process is described which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal or dielectric structure is substantially planar. The method of forming integrated circuits with this structure involves providing a silicon body (50, 51) and then forming a first insulating layer (52) on a major surface of the silicon body. A layer of polycrystalline silicon (53) is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer (55) is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions (56) on the major surface of the silicon body (50). The remaining polycrystalline silicon layer (53) is then removed by etching to leave the narrow dimensioned regions (56) on the major surfaces of the silicon body. A conductive layer is blanket desposited over the narrow dimensioned regions and areas in between. A blanket layer of a plastic material over the conductive layer to planarize the surface is accomplished. Reactive ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions (56) are reached leaving the structure of patterns (59 to 64) of metal filling the regions between the pattern of dielectric material having a thickness dimension in the order of a micron or less.

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