公开(公告)号：GB2633234A

公开(公告)日：2025-03-05

申请号：GB202416054

申请日：2023-03-30

Applicant: IBM

Inventor： ASHRAF ELSHARIF ,  RICHARD BRANCIFORTE ,  GREGORY ALEXANDER ,  DEANNA POSTLES DUNN BERGER ,  TIMOTHY BRONSON ,  AARON TSAI ,  TAYLOR PRITCHARD ,  MARKUS KALTENBACH ,  CHRISTIAN JACOBI ,  MICHAEL BLAKE

IPC: G06F12/0811 ,  G06F12/0897

Abstract: A computer system includes a processor core and a memory system in signal communication with the processor core. The memory system includes a first cache and a second cache. The first cache is arranged at a first level of a hierarchy in the memory system and is configured to store a plurality of first-cache entries. The second cache is arranged at a second level of the hierarchy that is lower than the first level, and stores a plurality of second-cache entries. The first cache maintains a directory that contains information for each of the first-cache entries. The second cache maintains a shadow pointer directory (SPD) that includes one or more SPD entries that maps each of the first-cache entries to a corresponding second cache entry at a lower-level cache location.

公开(公告)号：GB2630482A

公开(公告)日：2024-11-27

申请号：GB202411351

申请日：2023-01-09

Applicant: IBM

Inventor： LIOR BINYAMINI ,  LUDMILA ZERNAKOV ,  MARKUS KALTENBACH ,  CHUNG-LUNG SHUM ,  JANG-SOO LEE

IPC: G06F9/50 ,  G06F9/30

Abstract: A computer-implemented method includes assigning a first group of one or more units of an instruction pipeline of a processor as a frontend group and assigning a second group of the one or more units of the instruction pipeline of the processor as a backend group. A frontend logout is performed to transfer one or more trace records from the first group to a trace controller during an in-memory trace of an instruction. A backend logout is performed to transfer one or more trace records from the second group to the trace controller during the in-memory trace of the instruction. A next instruction is started in the first group of the instruction pipeline before the backend logout completes.