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公开(公告)号：EP0097158A4
公开(公告)日：1986-03-18
申请号：EP82900590
申请日：1981-12-30
Applicant: IBM
Inventor： MELTZER DAVID
CPC classification number: H03M13/13 , G06F11/1024
Abstract: Special control within a data processing system is signalled by a predetermined unique combination of data and error correcting code (ECC) bits. The predetermined combination, received from a source (1), is one which normally is decoded to indicate the presence of an uncorrectable error. A comparator (3) compares data bits held in a register (5) with a reference pattern of data bits held in a storage medium (7). At the same time, a syndrome generator (9) generates a syndrome from the received word, which syndrome is decoded by a syndrome decoder (11). If a particular flag syndrome sf (which is selected from the syndromes normally indicating the existence of an uncorrectable error) is detected, and comparator (3) indicates an equal comparison, AND (13) will provide a signal indicating that the unique combination has been received. It will also, through inverter (15) and AND (17) block transmission of an error indication to the system.
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公开(公告)号：WO2004004191A3
公开(公告)日：2004-04-29
申请号：PCT/US0320102
申请日：2003-06-24
Applicant: IBM
Inventor： GLOSSNER CLAIR JOHN III , HOKENEK ERDEM , MELTZER DAVID , MOUDGILL MAYAN
CPC classification number: G06F15/8084 , G06F9/345 , G06F9/3455 , G06F9/3887 , G06F15/8076 , G06F15/8092
Abstract: A digital signal processor (DSP) includes dual SIMD units that are connected in cascade, and wherein results of a first SIMD stage of the cascade may be stored in a register file of a second SIMD stage in the cascade. Each SIMD stage contains its own resources for storing operands and intermediate results (e.g., its own register file), as well as for decoding the operations that may be executed in that stage. Within each stage, hardware resources are organized to operate in SIMD manner, so that independent SIMD operations can be executed simultaneously, one in each stage of the cascade. Intermediate operands and results flowing through the cascade are stored at the register files of the stages, and may be accessed from those register files. Data may also be brought from memory directly into the register files of the stages in the cascade.
Abstract translation: 数字信号处理器（DSP）包括级联连接的双SIMD单元，并且级联的第一SIMD级的结果可以存储在级联中的第二SIMD级的寄存器文件中。 每个SIMD级包含其自己的用于存储操作数和中间结果（例如，它自己的寄存器文件）的资源，以及用于解码可能在该阶段中执行的操作。 在每个阶段中，硬件资源被组织为以SIMD方式操作，以便可以同时执行独立的SIMD操作，级联的每个阶段都有一个操作。 流经级联的中间操作数和结果存储在阶段的寄存器文件中，并且可以从这些寄存器文件访问。 数据也可能直接从内存中导入级联中的阶段的寄存器文件中。
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公开(公告)号：JPH11316681A
公开(公告)日：1999-11-16
申请号：JP2418899
申请日：1999-02-01
Applicant: IBM
Inventor： MELTZER DAVID , SILBERMAN JOEL ABRAHAM
Abstract: PROBLEM TO BE SOLVED: To execute loading to an instruction buffer of a super-scalar processor that can issue instructions at random by adding plural slots to the instruction buffer and filling an empty slot of an instruction with instructions given from an instruction cache if a first instruction is not included in a 1st slot of the instruction buffer. SOLUTION: A processor 10 which can issue instructions at random is equipped with an instruction cache 14 having plural cache rows. The cache 14 is connected to an instruction buffer via a multiplexer of an instruction unit 11. Plural slots of the instruction buffer are successively filled with instructions given from the cache 14 under the monitoring of the multiplexer. A slot including a first instruction is identified by a fetch address. If the first instruction is not included in a 1st slot of the instruction buffer, an optional empty slot of the instruction buffer is filled with instructions given from a subsequent cache row of the cache 14.
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公开(公告)号：JP2000003308A
公开(公告)日：2000-01-07
申请号：JP9622899
申请日：1999-04-02
Applicant: IBM
Inventor： DHONG SANG H , HALM PETER HOFSTAY , MELTZER DAVID , JOEL ABRAHAM SILVERMAN
IPC: G06F12/08
Abstract: PROBLEM TO BE SOLVED: To provide a method for realizing simultaneous, namely overlapped access to plural cache levels to reduce the waiting time of penalty of an upper level cache mistake. SOLUTION: The demand of a value (data or an instruction) is issued by a process 104 and is transferred to a lower level cache before it is decided whether a cache mistake of the value is generated at a cache of an upper level. In an execution configuration in which a lower level is an L2 cache, it is possible to directly supply a processor with a value. An address decoder operates at the upper level cache in parallel and can satisfy plural simultaneous memory demands. One of addresses (selected by order of priority logic on the basis of hit-miss information from the upper level cache) is gated to a work line driver of a memory array of the cache at the lower level by a multiplexer. Several bits among the address which do not need conversion from virtual into real can be immediately decoded.
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公开(公告)号：GB2365588B
公开(公告)日：2004-08-25
申请号：GB0103558
申请日：2001-02-14
Applicant: IBM
Inventor： GLOSSNER CLAIR JOHN , HOKENEK ERDEM , MELTZER DAVID , MOUDGILL MAVAN
Abstract: A system and method for processing operations that use data vectors each comprising a plurality of data elements, in accordance with the present invention, includes a vector data file comprising a plurality of storage elements for storing data elements of the data vectors. A pointer array is coupled by a bus to the vector data file. The pointer array includes a plurality of entries wherein each entry identifies at least one storage element in the vector data file. The at least one storage element stores at least one data element of the data vectors, wherein for at least one particular entry in the pointer array, the at least one storage element identified by the particular entry has an arbitrary starting address in the vector data file.
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Patent Agency Ranking6.发明专利
公开(公告)号：CA2444543A1
公开(公告)日：2002-11-07
申请号：CA2444543
申请日：2002-04-26
Applicant: IBM
Inventor： GLOSSNER CLAIR JOHN III , ALTMAN ERIK R , HOKENEK ERDEM , MELTZER DAVID , MOUDGILL MAYAN
IPC: G06F9/38
Abstract: A processor for processing a first instruction form and a second instruction form of an instruction set comprises execution units (301-305) connected to an instruction fetch unit (322) for the first instruction form and a sequencer (325) for the second instruction form. The processor comprises a decode unit (323) for decoding instructions of the first instruction form into control signals for the execution units (301-305), and buffers (306-310), proximate to the execution units (301-305), for storing predecoded instructions of the second instruction form.
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公开(公告)号：AU2003249378A8
公开(公告)日：2004-01-19
申请号：AU2003249378
申请日：2003-06-24
Applicant: IBM
Inventor： MELTZER DAVID , HOKENEK ERDEM , MOUDGILL MAYAN , GLOSSNER CLAIR JOHN III
Abstract: A digital signal processor (DSP) includes dual SIMD units that are connected in cascade, and wherein results of a first SIMD stage of the cascade may be stored in a register file of a second SIMD stage in the cascade. Each SIMD stage contains its own resources for storing operands and intermediate results (e.g., its own register file), as well as for decoding the operations that may be executed in that stage. Within each stage, hardware resources are organized to operate in SIMD manner, so that independent SIMD operations can be executed simultaneously, one in each stage of the cascade. Intermediate operands and results flowing through the cascade are stored at the register files of the stages, and may be accessed from those register files. Data may also be brought from memory directly into the register files of the stages in the cascade.
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公开(公告)号：CA2481567A1
公开(公告)日：2003-10-30
申请号：CA2481567
申请日：2002-04-19
Applicant: IBM
Inventor： ALTMAN ERIK R , MOUDGILL MAYAN , GLOSSNER CLAIR JOHN III , MELTZER DAVID , HOKENEK ERDEM
Abstract: A microprocessor includes a logic circuit. A selection device is coupled to the logic circuit, and the selection device procides switching of on/off states of the logic circuit based on a stored logical value. A program instruction is included which sets the stored logical value control the on/o ff states of the logic circuit based on anticipated usage of the logical circui t in accordance with an instruction sequence of the microprocessor.
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9.发明专利
公开(公告)号：DE3175912D1
公开(公告)日：1987-03-12
申请号：DE3175912
申请日：1981-02-16
Applicant: IBM
Inventor： MELTZER DAVID
Abstract: A data processing system is described comprising a cyclic bulk storage device attached to a CPU and a main storage through standard channel facilities including a channel control unit. The storage device is divided into a plurality of randomly accessible pages each page being subdivided into two sequentially and cyclically accessible Sectors 0 and Sector 1. Data is transferred byte by byte between a selected page of the device and a specified one-page data area (labelled Real Page) in the main storage. A channel program is constructed using three channel command words (CCWs); a Seek Page command (CCWI) followed by two different Read or Write commands CCW2, CCW3. At the end of the Seek Page operation, (CCWI) the control unit determines which of Sector 0 or 1 is more immediately accessible. If it is Sector 0 a branching control signal given to the channel causes the channel to chain to the second command CCW2, but if it is Sector 1, a different control signal given to the channel causes it to skip over the second command CCW2 and chain to the third command CCW3. When chained to the second command CCW2, the channel executes the transfer of one page of data in normal sequence, i. e. Sector 0 first and Sector 1 next. When chained to the third command CCW3, the channel executes the data transfer in reverse sequence, i.e. Sector 1 first and Sector 0 next. Such sector transfers are selectively controlled by indirect data address words (IDAWs) addressed by addresses IDAW1 and IDAW2 contained in the commands CCW2 and CCW3. Following transfer of a complete page, the control unit generates a signal combination causing the channel to chain to a first command CCW1 in a second program of three commands CCW1, 2 and 3.
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公开(公告)号：GB2365588A
公开(公告)日：2002-02-20
申请号：GB0103558
申请日：2001-02-14
Applicant: IBM
Inventor： GLOSSNER CLAIR JOHN , HOKENEK ERDEM , MELTZER DAVID , MOUDGILL MAVAN
Abstract: A system and method for processing operations that use data vectors each comprising a plurality of data elements, includes a vector data file 309 comprising a plurality of data storage elements (columns and rows) which store data vectors. A pointer array 202 is coupled via a bus to the vector data file. The pointer array includes a plurality of entries, each entry identifies at least one storage element in the vector data file. The at least one storage element stores at least one data element 311 of the data vectors, wherein for at least one particular entry in the pointer array, the at least one storage element identified by the particular entry has an arbitrary starting address 3,3 in the vector data file.
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