公开(公告)号：GB2565243A

公开(公告)日：2019-02-06

申请号：GB201816545

申请日：2017-02-24

Applicant: IBM

Inventor： EVANGELOS STAVROS ELEFTHERIOU ,  LUKAS KULL ,  ANGELIKI PANTAZI ,  ABU SEBASTIAN ,  TOMAS TUMA ,  MILOS STANISAVLJEVIC

IPC: G06N3/063

Abstract: Artificial neuron apparatus includes a resistive memory cell connected in an input circuit having a neuron input, for receiving neuron input signals, and a current source for supplying a read current to the cell. The input circuit is selectively configurable in response to a set of control signals, defining alternating read and write phases of operation, to apply the read current to the cell during the read phase and to apply a programming current to the cell, for programming cell resistance, on receipt of a neuron input signal during the write phase. The cell resistance is progressively changed from a first state to a second state in response to successive neuron input signals. The apparatus further includes an output circuit comprising a neuron output and a digital latch which is connected to the input circuit for receiving a measurement signal dependent on cell resistance.

公开(公告)号：GB2531756A

公开(公告)日：2016-05-04

申请号：GB201419240

申请日：2014-10-29

Applicant: IBM

Inventor： TOBIAS BLAETTLER ,  THOMAS MITTELHOLZER ,  NIKOLAOS PAPANDREOU ,  THOMAS PARNELL ,  CHARALAMPOS POZIDIS ,  MILOS STANISAVLJEVIC

IPC: G06F11/10

Abstract: A multi-chip device 100 for storing data comprises: a plurality of memory chips 10 adapted to store encoded input data 1, where each of the chips includes a detection unit adapted to perform a detection algorithm on the stored encoded input data for retrieving detected bits and to output the retrieved detected bits 3 and detection information 2 associated with the detection algorithm; an evaluation unit 20 adapted to perform an evaluation of the detection information from each of the plurality of memory chips, and to adapt the detection algorithm of any of the detection units depending on the performed evaluation; a combination unit 30 adapted to receive the detected bits and to combine the detected bits; and a decoding unit 40 adapted to output decoded data by decoding the combined detected bits 5. The detection algorithm may be threshold based detection algorithm, such as a drift invariant detection algorithm. The device may facilitate improved bit error rates at the output of an error correction code engine, which may be particularly useful for non-volatile memory.

公开(公告)号：GB2598526A

公开(公告)日：2022-03-02

申请号：GB202118254

申请日：2020-06-03

Applicant: IBM

Inventor： CHARLES CAMP ,  MILOS STANISAVLJEVIC ,  ROBERT ALLAN CYPRUS

IPC: H03M13/29 ,  H03M13/15

Abstract: A decoder for decoding a binary symmetry-invariant product code includes a data array having orthogonal first and second dimensions. The data array is configured to access a binary symmetry-invariant product code buffered therein along only the first dimension. The decoder also includes an error storage array for storing error locations and a first correction circuit configured to detect and correct errors in data accessed from the data array along the first dimension and to store error locations along the second dimension in the error storage array. The first correction circuit determines the error locations based on data symmetry of the symmetry-invariant product code. The decoder also includes a second correction circuit that, prior to receipt by the first correction circuit of data accessed from the data array along the first dimension, corrects the data accessed from the data array based on the error locations stored in the error storage array.

公开(公告)号：GB2598526B

公开(公告)日：2022-06-15

申请号：GB202118254

申请日：2020-06-03

Applicant: IBM

Inventor： CHARLES CAMP ,  MILOS STANISAVLJEVIC ,  ROBERT ALLAN CYPRUS

IPC: H03M13/29 ,  H03M13/15

Abstract: A decoder for decoding a binary symmetry-invariant product code includes a data array having orthogonal first and second dimensions. The data array is configured to access a binary symmetry-invariant product code buffered therein along only the first dimension. The decoder also includes an error storage array for storing error locations and a first correction circuit configured to detect and correct errors in data accessed from the data array along the first dimension and to store error locations along the second dimension in the error storage array. The first correction circuit determines the error locations based on data symmetry of the symmetry-invariant product code. The decoder also includes a second correction circuit that, prior to receipt by the first correction circuit of data accessed from the data array along the first dimension, corrects the data accessed from the data array based on the error locations stored in the error storage array.

公开(公告)号：GB2565243B

公开(公告)日：2019-07-31

申请号：GB201816545

申请日：2017-02-24

Applicant: IBM

Inventor： EVANGELOS STAVROS ELEFTHERIOU ,  LUKAS KULL ,  ANGELIKI PANTAZI ,  ABU SEBASTIAN ,  TOMAS TUMA ,  MILOS STANISAVLJEVIC

IPC: G06N3/063

Abstract: Artificial neuron apparatus includes a resistive memory cell connected in an input circuit having a neuron input, for receiving neuron input signals, and a current source for supplying a read current to the cell. The input circuit is selectively configurable in response to a set of control signals, defining alternating read and write phases of operation, to apply the read current to the cell during the read phase and to apply a programming current to the cell, for programming cell resistance, on receipt of a neuron input signal during the write phase. The cell resistance is progressively changed from a first state to a second state in response to successive neuron input signals. The apparatus further includes an output circuit comprising a neuron output and a digital latch which is connected to the input circuit for receiving a measurement signal dependent on cell resistance.