公开(公告)号：EP2100241A4

公开(公告)日：2011-01-12

申请号：EP07865741

申请日：2007-12-17

Applicant: IBM

Inventor： FIORENZA GIOVANNI ,  MURRAY CONAL E ,  RODBELL KENNETH P ,  TANG HENRY

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F2217/16

公开(公告)号：JP2007193795A

公开(公告)日：2007-08-02

申请号：JP2006351055

申请日：2006-12-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HABIB HICHRI ,  LU ANDREW ,  MURRAY CONAL E ,  MATTHEW S ANGYAL ,  MCHERRON DALE C ,  FIORENZA GIOVANNI

IPC: G06F17/50

CPC classification number: G06F17/50

Abstract: PROBLEM TO BE SOLVED: To provide a system, a method and a computer program for analyzing circuit design.
SOLUTION: This system, this method and this computer program for analyzing circuit design provide a means for discretizing a circuit pattern into a series of pixels. A fraction of at least one constituent material is determined for each pixel. A deflection is also determined for each pixel. The deflection is predicated upon a planarizing of the pixel, and it is calculated while utilizing an algorithm that includes the fraction of the at least one constituent material. A series of deflections for the series of pixels may be mapped and evaluated.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供用于分析电路设计的系统，方法和计算机程序。 解决方案：该系统，该方法和用于分析电路设计的该计算机程序提供了将电路图案离散成一系列像素的方法。 确定每个像素的至少一个构成材料的一部分。 还为每个像素确定偏转。 该偏转基于像素的平面化，并且在利用包括至少一个构成材料的分数的算法的同时进行计算。 可以映射和评估一系列像素的一系列偏转。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO2008082938A3

公开(公告)日：2008-12-11

申请号：PCT/US2007087766

申请日：2007-12-17

Applicant: IBM ,  FIORENZA GIOVANNI ,  MURRAY CONAL E ,  RODBELL KENNETH P ,  TANG HENRY

Inventor： FIORENZA GIOVANNI ,  MURRAY CONAL E ,  RODBELL KENNETH P ,  TANG HENRY

IPC: G06F17/50 ,  G06F7/62 ,  G06F19/00

CPC classification number: G06F17/5009 ,  G06F2217/16

Abstract: A method of determining a stopping power of a design structure with respect to a traveling particle. The method includes (i) providing design information of the design structure comprising a back-end-of-line layer which includes N interconnect layers, N being a positive integer, (ii) dividing each interconnect layer of the N interconnect layers into multiple pixels, and (iii) determining a first path of the traveling particle in a first interconnect layer of the N interconnect layers, (iv) identifying M path pixels of the multiple pixels of the first interconnect layer on the first path of the traveling particle, M being a positive integer, and (v) determining a first loss energy lost by the traveling particle due to its completely passing through a first pixel of the M path pixels.

Abstract translation: 确定设计结构相对于行进粒子的停止能力的方法。 该方法包括（i）提供设计结构的设计信息，该设计结构包括包含N个互连层的后端行层，N是正整数，（ii）将N个互连层中的每个互连层分成多个像素 （iii）确定N个互连层中的第一互连层中的行进粒子的第一路径，（iv）识别在行进粒子的第一路径上的第一互连层的多个像素的M个路径像素，M （v）确定由于其完全穿过M个路径像素的第一像素而由行进粒子损失的第一损失能量。

公开(公告)号：GB2491778A

公开(公告)日：2012-12-12

申请号：GB201217774

申请日：2011-03-23

Applicant: IBM

Inventor： COHEN GUY ,  MURRAY CONAL E ,  ROOKS MICHAEL J

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.

公开(公告)号：GB2513761B

公开(公告)日：2015-07-15

申请号：GB201413366

申请日：2012-12-19

Applicant: IBM

Inventor： COHEN GUY ,  GUILLORN MICHAEL A ,  MURRAY CONAL E

IPC: H01L29/66 ,  H01L29/775

公开(公告)号：GB2513761A

公开(公告)日：2014-11-05

申请号：GB201413366

申请日：2012-12-19

Applicant: IBM

Inventor： COHEN GUY ,  GUILLORN MICHAEL A ,  MURRAY CONAL E

IPC: H01L29/66 ,  H01L29/775

Abstract: A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.

公开(公告)号：GB2491778B

公开(公告)日：2014-03-12

申请号：GB201217774

申请日：2011-03-23

Applicant: IBM

Inventor： COHEN GUY ,  MURRAY CONAL E ,  ROOKS MICHAEL J

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.

公开(公告)号：DE112011100326T5

公开(公告)日：2012-10-31

申请号：DE112011100326

申请日：2011-03-23

Applicant: IBM

Inventor： COHEN GUY ,  MURRAY CONAL E ,  ROOKS MICHAEL J

IPC: H01L29/775

Abstract: Es werden Techniken zur Einbettung von Silicium-Germanium(e-SiGe)-Source- und Drain-Stressoren in nanoskaligen kanalbasierten Feldeffekttransistoren (FETs) bereitgestellt. Nach einem Aspekt der Erfindung beinhaltet ein Verfahren zum Herstellen eines FET die folgenden Schritte. Ein dotiertes Substrat mit einem darauf befindlichen Dielektrikum wird bereitgestellt. Mindestens ein Silicium-(Si-)Nanodraht wird auf dem Dielektrikum platziert. Ein oder mehrere Teile des Nanodrahtes werden mit einer Maske abgedeckt, wobei andere Teile des Nanodrahtes freiliegend bleiben. Epitaktisches Germanium (Ge) wird auf den freiliegenden Teilen des Nanodrahtes aufgewachsen. Das epitaktische Germanium wird in das Si im Nanodraht eindiffundiert, um die im Nanodraht eingebetteten SiGe-Zonen auszubilden, die die Druckspannung in den Nanodraht einbringen. Das dotierte Substrat dient als Gate des FET, die durch Maske abgedeckten Teile des Nanodrahtes dienen als Kanäle des FET, und die eingebetteten SiGe-Zonen dienen als Source- und Drain-Zonen des FET.