中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

6 records (took 0.01 seconds)

    REMOVABLE LINERS FOR CHARGED PARTICLE BEAM SYSTEMS
    1.
    发明申请
    REMOVABLE LINERS FOR CHARGED PARTICLE BEAM SYSTEMS 审中-公开
    带电粒子束系统的可拆卸衬垫

    公开(公告)号：WO2007065896B1

    公开(公告)日：2007-10-25

    申请号：PCT/EP2006069328

    申请日：2006-12-05

    Applicant: IBM ,  IBM UK ,  CHANDLER ALAN MICHAEL ,  DESAI TUSHAR ,  HAYFORD ELLIS CRAIG ,  MONE NICHOLAS JR ,  NAKOS JAMES SPIROS

    Inventor： CHANDLER ALAN MICHAEL ,  DESAI TUSHAR ,  HAYFORD ELLIS CRAIG ,  MONE NICHOLAS JR ,  NAKOS JAMES SPIROS

    IPC: H01J37/317 ,  H01J37/16

    CPC classification number: H01J37/3171 ,  H01J37/16 ,  H01J2237/0213 ,  H01J2237/022 ,  H01J2237/0268

    Abstract: An improved performance charged beam apparatus and method of improving the performance of charged beam apparatus are provided. The apparatus includes: a chamber having an interior surface; a pump port for evacuating the chamber (170) ; a substrate holder within the chamber (245) ; a charged particle beam within the chamber (250) , the charged beam generated by a source (130) and the charged particle beam striking the substrate; and one or more liners in contact with one or more different regions (A, B, C) of the interior surface of the chamber, the liners preventing material generated by interaction of the charged beam and the substrate from coating the one or more different regions of the interior surface of the chamber.

    Abstract translation: 提供改进的性能的电子束装置和改善电子束装置的性能的方法。 该设备包括：具有内表面的腔室; 用于排空腔室（170）的泵端口; 在腔室（245）内的衬底保持器; 腔室（250）内的带电粒子束，由源（130）产生的带电束和撞击衬底的带电粒子束; 以及与腔室的内表面的一个或多个不同区域（A，B，C）接触的一个或多个衬层，衬层防止由带电梁和衬底的相互作用产生的材料涂覆一个或多个不同区域 的室内表面。

    REMOVABLE LINERS FOR CHARGED PARTICLE BEAM SYSTEMS
    2.
    发明申请
    REMOVABLE LINERS FOR CHARGED PARTICLE BEAM SYSTEMS 审中-公开
    充电粒子束系统的可拆卸线

    公开(公告)号：WO2007065896A2

    公开(公告)日：2007-06-14

    申请号：PCT/EP2006069328

    申请日：2006-12-05

    Applicant: IBM ,  IBM UK ,  CHANDLER ALAN MICHAEL ,  DESAI TUSHAR ,  HAYFORD ELLIS CRAIG ,  MONE NICHOLAS JR ,  NAKOS JAMES SPIROS

    Inventor： CHANDLER ALAN MICHAEL ,  DESAI TUSHAR ,  HAYFORD ELLIS CRAIG ,  MONE NICHOLAS JR ,  NAKOS JAMES SPIROS

    CPC classification number: H01J37/3171 ,  H01J37/16 ,  H01J2237/0213 ,  H01J2237/022 ,  H01J2237/0268

    Abstract: An improved performance charged beam apparatus and method of improving the performance of charged beam apparatus are provided. The apparatus includes: a chamber having an interior surface; a pump port for evacuating the chamber; a substrate holder within the chamber; a charged particle beam within the chamber, the charged beam generated by a source and the charged particle beam striking the substrate; and one or more liners in contact with one or more different regions of the interior surface of the chamber, the liners preventing material generated by interaction of the charged beam and the substrate from coating the one or more different regions of the interior surface of the chamber.

    Abstract translation: 提供一种改进的性能充电束装置和提高带电束装置的性能的方法。 该装置包括：具有内表面的室; 用于抽空室的泵口; 腔室内的衬底保持器; 室内的带电粒子束，由源产生的带电束和带电粒子束撞击衬底; 以及与室的内表面的一个或多个不同区域接触的一个或多个衬垫，衬垫防止由带电束和衬底的相互作用产生的材料涂覆室的内表面的一个或多个不同区域 。

    METHOD OF FABRICATING A NITRIDED SILICON OXIDE GATE DIELECTRIC LAYER
    4.
    发明申请
    METHOD OF FABRICATING A NITRIDED SILICON OXIDE GATE DIELECTRIC LAYER 审中-公开
    制备氮化硅氧烷膜电介质层的方法

    公开(公告)号：WO2008055150A3

    公开(公告)日：2008-06-19

    申请号：PCT/US2007082988

    申请日：2007-10-30

    Applicant: IBM ,  ADAMS EDWARD DENNIS ,  BURNHAM JAY SANFORD ,  GOUSEV EVGENI ,  NAKOS JAMES SPIROS ,  PREUSS HEATHER ELIZABETH ,  SHEPARD JOSEPH FRANCIS

    Inventor： ADAMS EDWARD DENNIS ,  BURNHAM JAY SANFORD ,  GOUSEV EVGENI ,  NAKOS JAMES SPIROS ,  PREUSS HEATHER ELIZABETH ,  SHEPARD JOSEPH FRANCIS

    IPC: H01L21/31

    CPC classification number: H01L21/3144 ,  H01L21/28202

    Abstract: A method of forming a nitrided silicon oxide layer. The method includes: forming a silicon dioxide layer on a surface (32) of a silicon substrate (30); performing a rapid thermal nitridation of the silicon dioxide layer at a temperature of less than or equal to about 900 °C and a pressure greater than about 500 Torr to form an initial nitrided silicon oxide layer; and performing a rapid thermal oxidation or anneal of the initial nitrided silicon oxide layer at a temperature of less than or equal to about 900 °C and a pressure greater than about 500 Torr to form a nitrided silicon oxide layer (34). Also a method of forming a MOSFET with a nitrided silicon oxide dielectric layer (34).

    Abstract translation: 形成氮化硅氧化物层的方法。 该方法包括：在硅衬底（30）的表面（32）上形成二氧化硅层; 在小于或等于约900℃的温度和大于约500托的压力下进行二氧化硅层的快速热氮化，以形成初始氮化氧化硅层; 并且在小于或等于约900℃的温度和大于约500托的压力下进行初始氮化硅氧化物层的快速热氧化或退火以形成氮化二氧化硅层（34）。 还有一种用氮化硅氧化物介电层（34）形成MOSFET的方法。

    Triple polysilicon embedded vnram cell
    6.
    发明专利
    Triple polysilicon embedded vnram cell 未知

    公开(公告)号：GB2347016B

    公开(公告)日：2003-07-02

    申请号：GB0001002

    申请日：2000-01-18

    Applicant: IBM

    Inventor： LAM CHUNG HON ,  MILES GLEN ,  NAKOS JAMES SPIROS ,  WILLETS CHRISTA

    IPC: H01L21/8238 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8239

    Abstract: A logic chip including a non-volatile random access memory (NVRAM) array and method of fabrication thereof. The chip includes devices with gates on one or more of three polysilicon layers. Chip logic uses normal FETs and array support includes high voltage FETs. Both logic and support are CMOS. The gates of normal FETs in the chip logic are from the third, uppermost polysilicon layer. The third poly silicon layer also is used as a mask for high voltage FETs and array word lines, both of which use the second polysilicon layer for gates. The first polysilicon layer is used solely for cell floating gates.

Patent Agency Ranking