公开(公告)号：EP0772231A3

公开(公告)日：1998-09-30

申请号：EP96307629

申请日：1996-10-21

Applicant: IBM

Inventor： STAMPER ANTHONY KENDALL ,  LEBEL RICHARD JOHN ,  LANGDEAU GARY LIONEL

IPC: H01L21/205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L21/76889 ,  H01L21/28061 ,  H01L21/28518

Abstract: A method of forming low resistivity conductive lines on a semiconductor substrate is disclosed. In practicing the method a multichamber tool is used to advantage by forming a first doped polysilicon layer (14) on the surface of a substrate (12), forming a second undoped layer (16) on the doped layer (14), while maintaining the work piece under a vacuum environment, moving the substrate to a second chamber and thereafter forming a silicide containing layer (17) on the undoped polysilicon layer (16). Various techniques may be used to deposit either the polysilicon or the silicide layer such as sputtering may also be used.

公开(公告)号：EP2089169A4

公开(公告)日：2010-12-29

申请号：EP07853978

申请日：2007-10-12

Applicant: IBM

Inventor： CRANDAL COONEY EDWARD ,  MURPHY WILLIAM JOSEPH ,  STAMPER ANTHONY KENDALL ,  STRIPPE DAVID CRAIG

IPC: B08B5/00 ,  C25F1/00

CPC classification number: H01L21/67028 ,  H01J37/3244 ,  H01J37/32862 ,  H01L21/02063

公开(公告)号：WO2007131867B1

公开(公告)日：2008-03-06

申请号：PCT/EP2007054077

申请日：2007-04-25

Applicant: IBM ,  IBM UK ,  JAFFE MARK DAVID ,  DALTON TIMOTHY JOSEPH ,  GAMBINO JEFFREY PETER ,  KARTSCHOKE PAUL DAVID ,  STAMPER ANTHONY KENDALL ,  BERNSTEIN KERRY

Inventor： JAFFE MARK DAVID ,  DALTON TIMOTHY JOSEPH ,  GAMBINO JEFFREY PETER ,  KARTSCHOKE PAUL DAVID ,  STAMPER ANTHONY KENDALL ,  BERNSTEIN KERRY

IPC: H01L21/768 ,  H01L27/12

CPC classification number: H01L21/76898 ,  H01L21/768 ,  H01L21/84 ,  H01L23/481 ,  H01L23/522 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

Abstract translation: 具有相对侧的布线电平的半导体器件以及制造与相对侧的器件和布线电平接触的半导体结构的方法。 该方法包括在绝缘体上硅衬底上制造器件，其中器件的第一接触和第一侧的第一接触处的布线电平，去除下硅层以暴露所述掩埋氧化物层，形成第二触点到器件 通过掩埋氧化物层形成掩埋氧化物层上方的布线电平到第二触点。

公开(公告)号：EP2024997A4

公开(公告)日：2009-12-16

申请号：EP07797486

申请日：2007-05-16

Applicant: IBM

Inventor： BERNSTEIN KERRY ,  DALTON TIMOTHY JOSEPH ,  GAMBINO JEFFREY PETER ,  JAFFE MARK DAVID ,  KARTSCHOKE PAUL DAVID ,  LUCE STEPHEN ELLINWOOD ,  STAMPER ANTHONY KENDALL

IPC: H01L25/065 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5329 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：JP2002353729A

公开(公告)日：2002-12-06

申请号：JP2002101234

申请日：2002-04-03

Applicant: IBM

Inventor： BALLANTINE ARNE WATSON ,  EDELSTEIN DANIEL CHARLES ,  NAKOS JAMES SPIROS ,  STAMPER ANTHONY KENDALL

IPC: H01Q21/28 ,  H01P11/00 ,  H01Q1/22 ,  H01Q1/38 ,  H01Q13/02 ,  H01Q13/06

Abstract: PROBLEM TO BE SOLVED: To provide a method for fabricating a horn antenna device within an integrated circuit chip. SOLUTION: The horn antenna device 100 includes a metallic horn structure 10 with a wide aperture, that is, a horizontal waveguide. The horizontal waveguide has a tapered via that electromagnetically communicates with a vertical waveguide structure 60 to transmit energy to and from an electronic sub-component 40 configuring part of IC chips 5. Dual damascene processing is used to fabricate the horn antenna device within the IC chip.

公开(公告)号：WO2007137049A3

公开(公告)日：2008-01-31

申请号：PCT/US2007069002

申请日：2007-05-16

Applicant: IBM ,  BERNSTEIN KERRY ,  DALTON TIMOTHY JOSEPH ,  GAMBINO JEFFREY PETER ,  JAFFE MARK DAVID ,  KARTSCHOKE PAUL DAVID ,  LUCE STEPHEN ELLINWOOD ,  STAMPER ANTHONY KENDALL

Inventor： BERNSTEIN KERRY ,  DALTON TIMOTHY JOSEPH ,  GAMBINO JEFFREY PETER ,  JAFFE MARK DAVID ,  KARTSCHOKE PAUL DAVID ,  LUCE STEPHEN ELLINWOOD ,  STAMPER ANTHONY KENDALL

IPC: H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5329 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon (110A and 110B) from two silicon-on- insulator wafers (110A and 100B), respectively, having devices (130A and 130B), respectively, fabricated therein and bonding them back to back utilizing the buried oxide layers (115). Contacts (210) are then formed in the upper wafer (I00B) to devices (130A) in the lower wafer (100A) and wiring levels (170) are formed on the upper wafer (100B). The lower wafer (100A) may include wiring levels (170). The lower wafer (100A) may include landing pads (230) for the contacts. Contacts to the silicon layer (120) of the lower wafer (100A) may be silicided.

Abstract translation: 一种半导体结构及其制造方法。 该方法包括从分别制造在其中的器件（130A和130B）的两个绝缘体上硅晶片（110A和100​​B）去除后侧硅（110A和110B），并使用掩埋氧化物 层（115）。 接触件（210）然后在上晶片（I00B）中形成在下晶片（100A）中的器件（130A），并且布线层（170）形成在上晶片（100B）上。 下晶片（100A）可以包括布线​​层（170）。 下晶片（100A）可以包括用于触点的着陆焊盘（230）。 与下晶片（100A）的硅层（120）的接触可以被硅化。

公开(公告)号：DE69632375T2

公开(公告)日：2006-01-19

申请号：DE69632375

申请日：1996-10-21

Applicant: IBM

Inventor： STAMPER ANTHONY KENDALL ,  LEBEL RICHARD JOHN ,  LANGDEAU GARY LIONEL

IPC: H01L21/205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768

Abstract: A method of forming low resistivity conductive lines on a semiconductor substrate is disclosed. In practicing the method a multichamber tool is used to advantage by forming a first doped polysilicon layer on the surface of a substrate, forming a second undoped layer on the doped layer, while maintaining the work piece under a vacuum environment, moving the substrate to a second chamber and thereafter forming a silicide containing layer on the undoped polysilicon layer. various techniques may be used to deposit either the polysilicon or the silicide layer such as sputtering may also be used. Practice of the method eliminates separation of silicide from polysilicon and increases product yield.

公开(公告)号：DE69632375D1

公开(公告)日：2004-06-09

申请号：DE69632375

申请日：1996-10-21

Applicant: IBM

Inventor： STAMPER ANTHONY KENDALL ,  LEBEL RICHARD JOHN ,  LANGDEAU GARY LIONEL

IPC: H01L21/205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768

Abstract: A method of forming low resistivity conductive lines on a semiconductor substrate is disclosed. In practicing the method a multichamber tool is used to advantage by forming a first doped polysilicon layer on the surface of a substrate, forming a second undoped layer on the doped layer, while maintaining the work piece under a vacuum environment, moving the substrate to a second chamber and thereafter forming a silicide containing layer on the undoped polysilicon layer. various techniques may be used to deposit either the polysilicon or the silicide layer such as sputtering may also be used. Practice of the method eliminates separation of silicide from polysilicon and increases product yield.

公开(公告)号：SG55222A1

公开(公告)日：1998-12-21

申请号：SG1996010424

申请日：1996-08-02

Applicant: IBM

Inventor： STAMPER ANTHONY KENDALL ,  LEBEL RICHARD JOHN ,  LANGDEAU GARY LIONEL

IPC: H01L21/205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/36

Abstract: A method of forming low resistivity conductive lines on a semiconductor substrate is disclosed. In practicing the method a multichamber tool is used to advantage by forming a first doped polysilicon layer on the surface of a substrate, forming a second undoped layer on the doped layer, while maintaining the work piece under a vacuum environment, moving the substrate to a second chamber and thereafter forming a silicide containing layer on the undoped polysilicon layer. various techniques may be used to deposit either the polysilicon or the silicide layer such as sputtering may also be used. Practice of the method eliminates separation of silicide from polysilicon and increases product yield.