公开(公告)号：EP1805796A4

公开(公告)日：2008-10-01

申请号：EP05800298

申请日：2005-09-29

Applicant: IBM ,  TOSHIBA KK

Inventor： CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  OH SANG-HYUN ,  PANDA SIDDHARTHA ,  RAUSCH WERNER A ,  SATO TSUTOMU ,  UTOMO HENRY K

IPC: H01L21/8238 ,  H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28079 ,  H01L21/7624 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A field effect transistor (FET) (10) is provided which includes a gate stack (29), a pair of first spacers (32) disposed over sidewalls of the gate stack (29 and a pair of semiconductor alloy regions (39) disposed on opposite sides of and spaced a first distance from the gate stack (29). Source and drain regions (24) of the FET (10) are at least partly disposed in the semiconductor alloy regions (39; and spaced a second distance from the gate stack (29) by a corresponding spacer of the pair of first spacers (32), which may be different from the first distance. The FET (10) may also include second spacers (34) disposed on the first spacers (32), and silicide regions (40) at least partly overlying the semiconductor alloy regions (39), wherein the silicide regions (40) are spacec from the gate stack (29) by the first and second spacers (32, 34).

公开(公告)号：WO2004053922A3

公开(公告)日：2004-09-10

申请号：PCT/GB0305265

申请日：2003-12-02

Applicant: IBM ,  IBM UK

Inventor： WISE RICHARD ,  YAN HONGWEN ,  JI BRIAN ,  PANDA SIDDHARTHA ,  CHEN BOMY

IPC: H01J37/32

CPC classification number: H01J37/32623 ,  H01J37/3266

Abstract: A plasma etching system having a wafer chuck with a magnet that applies a magnetic field over a wafer to shield the wafer from charged particles. The magnetic field is parallel with the wafer, and is strongest near the wafer surface. The magnetic field may be straight, or circular. In operation, electrons are deflected from the wafer by the Lorentz force, the wafer acquires a positive charge, and ions are deflected by electrostatic repulsion. Neutral species are allowed through the magnetic field, and they collide with the wafer. Neutral species generally provide more isotropic and material-selective etching than charged particles, so the present magnetic field tends to increase etch isotropy and material selectivity. Also, the magnetic field can protect the wafer from seasoning processes designed to clean unwanted films from the chamber surface as seasoning processes typically rely on etching by charged particles

Abstract translation: 一种等离子体蚀刻系统，其具有带磁体的晶圆吸盘，该磁体在晶圆上施加磁场以将晶圆从带电粒子屏蔽。 磁场与晶圆平行，在晶圆表面附近最强。 磁场可以是直的，也可以是圆形的。 在操作中，电子通过洛伦兹力从晶片偏转，晶片获得正电荷，并且离子通过静电排斥偏转。 允许中性物质通过磁场，并与晶圆碰撞。 中性物质通常提供比带电粒子更多的各向同性和材料选择性蚀刻，因此目前的磁场倾向于增加蚀刻各向同性和材料选择性。 而且，磁场可以保护晶片避免设计成从腔室表面清洗不需要的膜的调味过程，因为调味过程通常依赖于带电粒子的蚀刻

公开(公告)号：JP2010251799A

公开(公告)日：2010-11-04

申请号：JP2010167117

申请日：2010-07-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： WISE RICHARD ,  YAN HONGWEN ,  JI BRIAN ,  PANDA SIDDHARTHA ,  CHEN BOMY

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/304

CPC classification number: H01J37/32623 ,  H01J37/3266

Abstract: PROBLEM TO BE SOLVED: To provide a plasma etching system having a wafer chuck including a magnet that applies a magnetic field over a wafer to shield the wafer from charged particles.
SOLUTION: The magnetic field is parallel to the wafer, and the intensity thereof is highest near the wafer surface. The magnetic field may be straight, or circular. In operation, electrons are deflected from the wafer by the Lorentz force, the wafer is positively charged, and ions are deflected by electrostatic repulsion. Neutral chemical species are allowed to pass through the magnetic field, and collide with the wafer. Neutral chemical species generally provide higher isotropic and material-selective etching than charged particles, so that this magnetic field tends to increase etching isotropy and material selectivity. The magnetic field can protect the wafer from seasoning processes designed to remove unwanted films from the chamber surface because seasoning processes generally rely on etching by charged particles.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有晶片卡盘的等离子体蚀刻系统，该晶片卡盘包括在晶片上施加磁场以使晶片免受带电粒子的磁体。

解决方案：磁场平行于晶片，其强度在晶片表面附近最高。 磁场可以是直的或圆形的。 在操作中，电子通过洛仑兹力从晶片偏转，晶片带正电，离子被静电排斥偏转。 允许中性化学物质通过磁场，并与晶片碰撞。 中性化学物质通常提供比带电粒子更高的各向同性和材料选择性蚀刻，使得该磁场倾向于增加蚀刻各向同性和材料选择性。 磁场可以保护晶片免受设计用于从腔室表面去除不需要的膜的调味过程，因为调味过程通常依赖于带电粒子的蚀刻。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2004214630A

公开(公告)日：2004-07-29

申请号：JP2003396388

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RICHARD WISE ,  MARK C HEIKY ,  PANDA SIDDHARTHA ,  CHEN BOMY A

IPC: H05H1/46 ,  C23C16/513 ,  H01J37/32 ,  H01L21/00 ,  H01L21/205 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01J37/32192 ,  H01J37/32357 ,  H01L21/308

Abstract: PROBLEM TO BE SOLVED: To provide a system for effectively separating the reactivity of a gaseous phase reactant and the chemical reaction of a wafer surface. SOLUTION: A processing system, based on previously loaded plasma, is provided with a preliminary reaction plasma processing chamber, a power source connected to the preliminary reaction plasma processing chamber so as to drive the chamber and a wafer plasma processing chamber connected to the preliminary reaction plasma processing chamber through fluid. The preliminary reaction plasma processing chamber is constituted so as to generate reaction radicals, by subjecting to chemical reaction based on the plasma of a reaction substance. The wafer plasma processing chamber is constituted so as to allow reaction radicals to react with the seeds on the surface of a wafer arranged in the wafer plasma processing chamber. Another example includes a method for processing a wafer in a plasma environment, pre-loading a reactive gaseous flow and previously preventing the erosion of a wafer mask or an etching stop layer. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2002367960A

公开(公告)日：2002-12-20

申请号：JP2002161955

申请日：2002-06-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： MATHAD GANGADHARA S ,  PANDA SIDDHARTHA ,  RANADE RAJLV M

IPC: B44C1/22 ,  C03C25/68 ,  C23F1/00 ,  H01L21/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/762

CPC classification number: H01L21/30655 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/76224

Abstract: PROBLEM TO BE SOLVED: To provide a method of etching an opening having a high aspect ratio in a silicon substrate.
SOLUTION: This method comprises a process of etching a substrate with a first plasma formed using a first gas mixture including a bromo-contained gas, an oxygen-contained gas, and a first fluorine-contained gas. In this etching process, a side wall protecting attachment 24 is formed with the attachment accumulated near the entrance of an opening 14. In order to reduce the accumulation and increase the average etch rate, the side wall protecting attachment is made thinner periodically by forming a second plasma using a mixture containing silane and a second fluorine-contained gas. Over the entire process, the substrate is held in the same plasma reaction chamber, and the plasma is continuously retained in the process for making the side wall protecting attachment thinner. A trench having a depth larger than 40 times the width can be formed using a repetition cycle of etching and the process of making the side wall protecting attachment thinner.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种在硅衬底中蚀刻具有高纵横比的开口的方法。 解决方案：该方法包括使用包含含溴气体，含氧气体和第一含氟气体的第一气体混合物形成的第一等离子体来蚀刻基板的工艺。 在该蚀刻工艺中，形成侧壁保护附件24，其中附件积聚在开口14的入口附近。为了减少累积并增加平均蚀刻速率，侧壁保护附件通过形成 使用含有硅烷和第二含氟气体的混合物的第二等离子体。 在整个过程中，衬底保持在相同的等离子体反应室中，等离子体被连续地保留在使侧壁保护附着物更薄的过程中。 可以使用蚀刻的重复循环形成深度大于宽度的40倍的沟槽，并且使侧壁保护附着物的工艺变薄。

公开(公告)号：WO2004097909A2

公开(公告)日：2004-11-11

申请号：PCT/US2004011162

申请日：2004-04-12

Applicant: TOKYO ELECTRON LTD ,  IBM ,  PANDA SIDDHARTHA ,  MOSDEN AELAN ,  WISE RICH ,  SUGIYAMA KENRO ,  CAMILLERI JOSEPH GREGORY

Inventor： PANDA SIDDHARTHA ,  MOSDEN AELAN ,  WISE RICH ,  SUGIYAMA KENRO ,  CAMILLERI JOSEPH GREGORY

IPC: C23C14/00 ,  C23C14/32 ,  H01B13/00 ,  H01J37/32 ,  H01L21/00 ,  H01L21/3065 ,  H01L21/334

CPC classification number: H01L21/67069 ,  H01J37/32082 ,  H01J37/32165 ,  H01J37/3266 ,  H01L21/3065 ,  H01L29/66181

Abstract: A method and system for deep trench silicon etch is presented. The method comprises introducing a reactive process gas and a Noble gas to a plasma processing system, wherein the reactive process gas comprises two or more of HBr, a fluorine-containing gas, and O2, and the Noble gas comprises at least one of He, Ne, Ar, Xe, Kr, and Rn. Additionally, radio frequency (RF) power is applied to the substrate holder, upon which the substrate rests, at two different frequencies. The first RF frequency is greater than 10 MHz, and the second frequency is less than 10 MHz.

Abstract translation: 提出了深沟槽硅蚀刻的方法和系统。 该方法包括将反应性工艺气体和贵重气体引入等离子体处理系统，其中反应性工艺气体包括HBr，含氟气体和O 2中的两种或更多种，并且贵金属气体包括He， Ne，Ar，Xe，Kr和Rn。 此外，射频（RF）功率被施加到衬底搁置的衬底保持器上，处于两个不同的频率。 第一RF频率大于10MHz，第二频率小于10MHz。

公开(公告)号：SG142307A1

公开(公告)日：2008-05-28

申请号：SG2008029332

申请日：2005-09-29

Applicant: IBM ,  TOSHIBA KK

Inventor： CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  OH SANG-HYUN ,  PANDA SIDDHARTHA ,  RAUSCH WERNER A ,  SATO TSUTOMU ,  UTOMO HENRY K

Abstract: STRAINED CHANNEL FIELD EFFECT TRANSISTOR USING SACRIFICIAL SPACER A field effect transistor (FET) (10) is provided which includes a gate stack (29), a pair of first spacers (32) disposed over sidewalls of the gate stack (29) and a pair of semiconductor alloy regions (39) disposed on opposite sides of and spaced a first distance from the gate stack (29). Source and drain regions (24) of the FET (10) are at least partly disposed in the semiconductor alloy regions (39); and spaced a second distance from the gate stack (29) by a corresponding spacer of the pair of first spacers (32), which may be different from the first distance. The FET (10) may also include second spacers (34) disposed on the first spacers (32), and silicide regions (40) at least partly overlying the semiconductor alloy regions (39), wherein the silicide regions (40) are spaced from the gate stack (29) by the first and second spacers (32, 34).

公开(公告)号：SG132629A1

公开(公告)日：2007-06-28

申请号：SG2006079735

申请日：2006-11-16

Applicant: IBM ,  CHARTERED SEMICONDUCTOR MFG

Inventor： GREENE BRIAN JOSEPH ,  TEH YOUNG WAY ,  RIM KERN ,  LIN WENHE ,  PANDA SIDDHARTHA ,  LAI CHUNG WOH ,  LEE YONG MENG

Abstract: A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer (201) and a nitride layer (202).

公开(公告)号：SG138522A1

公开(公告)日：2008-01-28

申请号：SG2007030810

申请日：2007-04-27

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： ZHIJIONG LUO ,  NG HUNG Y ,  ROVEDO NIVO ,  NGUYEN PHUNG T ,  WILLE WILLIAM C ,  LINSAY RICHARD ,  LUN ZHAO ,  FU CHONG YUNG ,  PANDA SIDDHARTHA

Abstract: A semiconductor structure includes a base semiconductor substrate having a doped region located therein, and an epitaxial region located over the doped region. The semiconductor structure also includes a final isolation region located with the doped region and the epitaxial region. The final isolation region has a greater linewidth within the doped region than within the epitaxial region. A method for fabricating the semiconductor structure provides for forming the doped region prior to the epitaxial region. The doped region may be formed with reduced well implant energy and reduced lateral straggle. The final isolation region with the variable linewidth provides a greater effective isolation depth than an actual trench isolation depth.

公开(公告)号：AU2003285581A1

公开(公告)日：2004-06-30

申请号：AU2003285581

申请日：2003-12-02

Applicant: IBM

Inventor： WISE RICHARD ,  YAN HONGWEN ,  JI BRIAN ,  PANDA SIDDHARTHA ,  CHEN BOMY

IPC: H01J37/32

Abstract: A plasma etching system having a wafer chuck with a magnet that applies a magnetic field over a wafer to shield the wafer from charged particles. The magnetic field is parallel with the wafer, and is strongest near the wafer surface. The magnetic field may be straight, or circular. In operation, electrons are deflected from the wafer by the Lorentz force, the wafer acquires a positive charge, and ions are deflected by electrostatic repulsion. Neutral species are allowed through the magnetic field, and they collide with the wafer. Neutral species generally provide more isotropic and material-selective etching than charged particles, so the present magnetic field tends to increase etch isotropy and material selectivity. Also, the magnetic field can protect the wafer from seasoning processes designed to clean unwanted films from the chamber surface as seasoning processes typically rely on etching by charged particles.