公开(公告)号：EP2377148A4

公开(公告)日：2016-03-16

申请号：EP09836605

申请日：2009-11-19

Applicant: IBM ,  FREESCALE SEMICONDUCTOR INC

Inventor： RAMACHANDRAN RAVIKUMAR ,  YAN HONGWEN ,  MOUMEN NAIM ,  SCHAEFFER JAMES KENYON ,  KRISHNAN SIDDARTH A ,  WONG KEITH KWONG HON ,  KWON UNOH ,  BELYANSKY MICHAEL P ,  WISE RICHARD

IPC: H01L21/3205 ,  H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/823857

公开(公告)号：WO2004053922A3

公开(公告)日：2004-09-10

申请号：PCT/GB0305265

申请日：2003-12-02

Applicant: IBM ,  IBM UK

Inventor： WISE RICHARD ,  YAN HONGWEN ,  JI BRIAN ,  PANDA SIDDHARTHA ,  CHEN BOMY

IPC: H01J37/32

CPC classification number: H01J37/32623 ,  H01J37/3266

Abstract: A plasma etching system having a wafer chuck with a magnet that applies a magnetic field over a wafer to shield the wafer from charged particles. The magnetic field is parallel with the wafer, and is strongest near the wafer surface. The magnetic field may be straight, or circular. In operation, electrons are deflected from the wafer by the Lorentz force, the wafer acquires a positive charge, and ions are deflected by electrostatic repulsion. Neutral species are allowed through the magnetic field, and they collide with the wafer. Neutral species generally provide more isotropic and material-selective etching than charged particles, so the present magnetic field tends to increase etch isotropy and material selectivity. Also, the magnetic field can protect the wafer from seasoning processes designed to clean unwanted films from the chamber surface as seasoning processes typically rely on etching by charged particles

Abstract translation: 一种等离子体蚀刻系统，其具有带磁体的晶圆吸盘，该磁体在晶圆上施加磁场以将晶圆从带电粒子屏蔽。 磁场与晶圆平行，在晶圆表面附近最强。 磁场可以是直的，也可以是圆形的。 在操作中，电子通过洛伦兹力从晶片偏转，晶片获得正电荷，并且离子通过静电排斥偏转。 允许中性物质通过磁场，并与晶圆碰撞。 中性物质通常提供比带电粒子更多的各向同性和材料选择性蚀刻，因此目前的磁场倾向于增加蚀刻各向同性和材料选择性。 而且，磁场可以保护晶片避免设计成从腔室表面清洗不需要的膜的调味过程，因为调味过程通常依赖于带电粒子的蚀刻

公开(公告)号：JP2010251799A

公开(公告)日：2010-11-04

申请号：JP2010167117

申请日：2010-07-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： WISE RICHARD ,  YAN HONGWEN ,  JI BRIAN ,  PANDA SIDDHARTHA ,  CHEN BOMY

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/304

CPC classification number: H01J37/32623 ,  H01J37/3266

Abstract: PROBLEM TO BE SOLVED: To provide a plasma etching system having a wafer chuck including a magnet that applies a magnetic field over a wafer to shield the wafer from charged particles.
SOLUTION: The magnetic field is parallel to the wafer, and the intensity thereof is highest near the wafer surface. The magnetic field may be straight, or circular. In operation, electrons are deflected from the wafer by the Lorentz force, the wafer is positively charged, and ions are deflected by electrostatic repulsion. Neutral chemical species are allowed to pass through the magnetic field, and collide with the wafer. Neutral chemical species generally provide higher isotropic and material-selective etching than charged particles, so that this magnetic field tends to increase etching isotropy and material selectivity. The magnetic field can protect the wafer from seasoning processes designed to remove unwanted films from the chamber surface because seasoning processes generally rely on etching by charged particles.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有晶片卡盘的等离子体蚀刻系统，该晶片卡盘包括在晶片上施加磁场以使晶片免受带电粒子的磁体。

解决方案：磁场平行于晶片，其强度在晶片表面附近最高。 磁场可以是直的或圆形的。 在操作中，电子通过洛仑兹力从晶片偏转，晶片带正电，离子被静电排斥偏转。 允许中性化学物质通过磁场，并与晶片碰撞。 中性化学物质通常提供比带电粒子更高的各向同性和材料选择性蚀刻，使得该磁场倾向于增加蚀刻各向同性和材料选择性。 磁场可以保护晶片免受设计用于从腔室表面去除不需要的膜的调味过程，因为调味过程通常依赖于带电粒子的蚀刻。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：WO0184235A2

公开(公告)日：2001-11-08

申请号：PCT/US0111696

申请日：2001-04-10

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： BUKOFSKY SCOTT J ,  KUNKEL GERHARD ,  WISE RICHARD ,  WONG ALFRED

IPC: G03F1/00 ,  G03F7/20 ,  G03F

CPC classification number: G03F7/70466 ,  G03F7/203

Abstract: A method for exposing a workpiece in a dual exposure step-and-repeat process starts by forming a design for a reticle mask. Deconstruct the design for the reticle mask by removing a set(s) of the features that are juxtaposed to form hollow polygonally-shaped clusters with a gap in the center. Form unexposed resist on the workpiece. Load the workpiece and the reticle mask into the stepper. Expose the workpiece through the reticle mask. Reposition the workpiece by a nanostep. Then expose the workpiece through the reticle mask after the repositioning. Test whether the plural exposure process is finished. If the result of the test is NO the process loops back to repeat some of the above steps. Otherwise the process has been completed. An overlay mark is produced by plural exposures of a single mark. A dead zone is provided surrounding an array region in which printing occurs subsequent to exposure in an original exposure. Alternatively, the workpiece can be fully exposed first by stepping a series of full steps, then going back to the starting position, making a nanostep to reset the starting position and re-exposing from the reset starting position in the same way with full steps from the nanostepped position. The clusters may be in the shape of a hexagon or a diamond.

Abstract translation: 用于在双重曝光步骤和重复过程中曝光工件的方法通过形成掩模版掩模的设计而开始。 通过移除一些并列的特征来形成掩模版掩模的设计，以形成具有中心间隙的中空多边形簇。 在工件上形成未曝光的抗蚀剂。 将工件和掩模版掩模装入步进器。 通过掩模掩模将工件暴露。 用纳秒级重新定位工件。 然后在重新定位后将工件暴露在掩模版掩模之外。 测试多次曝光过程是否完成。 如果测试结果为“否”，则过程循环返回以重复上述步骤。 否则该过程已经完成。 通过单个标记的多次曝光产生重叠标记。 围绕阵列区域提供死区，其中在原始曝光中曝光之后发生印刷。 或者，可以通过步进一系列完整的步骤，然后返回到起始位置，首先完全暴露工件，从而使得纳秒能够以相同的方式从复位起始位置复位起始位置并再次曝光 纳米级位置。 簇可以是六边形或菱形的形状。

公开(公告)号：DE10352070A1

公开(公告)日：2004-05-27

申请号：DE10352070

申请日：2003-11-07

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DOBUZINSKY DAVID ,  PANDA SIDDHARTHA ,  WEIS ROLF ,  WISE RICHARD

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/461 ,  H01L21/68 ,  H01L21/8242

Abstract: A method is disclosed for improving etch uniformity in deep silicon etching of a monocrystalline silicon wafer. Such method includes forming a pad dielectric layer on a wafer including monocrystalline silicon, forming a silicon layer over the pad dielectric layer, and then applying a clamp to an edge of the wafer. The silicon layer is then removed except in areas protected by the clamp. Thereafter, a hardmask layer is applied and patterned on the wafer; and the wafer is then directionally etched with the patterned hardmask to etch trenches in the monocrystalline silicon.In such manner, a source of silicon (in the silicon layer) is provided at the wafer edge, such that the silicon loading is improved. In addition, the silicon layer at the wafer edge forms a blocking layer which prevents formation of black silicon.

公开(公告)号：AU2003285581A1

公开(公告)日：2004-06-30

申请号：AU2003285581

申请日：2003-12-02

Applicant: IBM

Inventor： WISE RICHARD ,  YAN HONGWEN ,  JI BRIAN ,  PANDA SIDDHARTHA ,  CHEN BOMY

IPC: H01J37/32

Abstract: A plasma etching system having a wafer chuck with a magnet that applies a magnetic field over a wafer to shield the wafer from charged particles. The magnetic field is parallel with the wafer, and is strongest near the wafer surface. The magnetic field may be straight, or circular. In operation, electrons are deflected from the wafer by the Lorentz force, the wafer acquires a positive charge, and ions are deflected by electrostatic repulsion. Neutral species are allowed through the magnetic field, and they collide with the wafer. Neutral species generally provide more isotropic and material-selective etching than charged particles, so the present magnetic field tends to increase etch isotropy and material selectivity. Also, the magnetic field can protect the wafer from seasoning processes designed to clean unwanted films from the chamber surface as seasoning processes typically rely on etching by charged particles.

公开(公告)号：AT504079T

公开(公告)日：2011-04-15

申请号：AT05746299

申请日：2005-04-21

Applicant: IBM

Inventor： WISE RICHARD ,  CHEN BOMY ,  HAKEY MARK ,  YAN HONGWEN

IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated from the sidewalls by the spacers. The spacers are then removed, forming air gaps at the sidewalls so that the conductors are separated from the sidewalls by the air gaps. Dielectric layers above and below the conductors may be low-k dielectrics having a dielectric constant less than that of the dielectric between the conductors. A cross-section of each of the conductors has a bottom in contact with the a low-k dielectric layer, a top in contact with another low-k dielectric, and sides in contact only with the air gaps. The air gaps serve to reduce the intralevel capacitance.