公开(公告)号：GB2527318A

公开(公告)日：2015-12-23

申请号：GB201410808

申请日：2014-06-17

Applicant: IBM

Inventor： MITTELHOLZER THOMAS ,  PAPANDREOU NIKOLAOS ,  PARNELL THOMAS ,  POZIDIS CHARALAMPOS ,  STANISAVLJEVIC MILOS

IPC: G11C11/56 ,  G06F11/10 ,  G11C13/00 ,  G11C16/26

Abstract: Apparatus and method for determining level-thresholds (5 figure 1) for q-level (multi level) memory cells such as NAND FLASH or Phase Change Memory cells. A group of the memory cells are read to obtain respective read signal components 20. The read signal components are processed in dependence on signal level 21 to produce a signal level vector (figure 3), comprising a series of elements, indicative of the distribution of read signal components in order of signal level. A plurality of possible sets of q−1 elements corresponding, respectively, to q−1 level-thresholds which partition the signal level vector into q segments, is then defined 22. The q−1 level-thresholds for the group of memory cells are then determined by selecting from the possible sets that set for which a predetermined difference function 23, dependent on differences in signal level for elements in each of said q segments for the set, has an optimum value. For example the difference function may be dependent on differences in signal level of the elements within the q segments and the optimum threshold values chosen would be based on minimizing the overall difference values between all considered elements. The first and second threshold estimation process may include hierarchical dichotomization. A computer program method for the implementation of the threshold estimation method is also included.

公开(公告)号：GB2530043A

公开(公告)日：2016-03-16

申请号：GB201415951

申请日：2014-09-10

Applicant: IBM

Inventor： BLAETTLER TOBIAS ,  MITTELHOLZER THOMAS ,  PAPANDREOU NIKOLAOS ,  PARNELL THOMAS ,  POZIDIS CHARALAMPOS ,  STANISAVLJEVIC MILOS

IPC: G11C13/00 ,  G06F11/10 ,  G06F12/02 ,  G11C11/56 ,  G11C16/34 ,  G11C29/26

Abstract: A device 10 and method for storing data in a plurality of multi-level cell (MLC) memory chips 21; each of the multi-level cell memory chips 21 comprising memory cells having a plurality of programmable levels. The device comprises a scrambling unit which generates a plurality of candidate scrambled sequences of data by performing a plurality of scrambling operations on a sequence of data to be stored; a calculation unit which evaluates or calculates a cost function (efficiency metric) for each of the candidate scrambled sequences of data, the result of each of the cost functions being indicative of a balancing degree of sub-sequences of a candidate scrambled sequence, when the sub-sequences of the candidate scrambled sequence are written to the plurality of multi-level cell memory chips; a selection unit which selects one of the candidate scrambled sequences of data based on the results of the calculated cost functions; and a storing unit which stores the selected candidate scrambled sequence of data in the plurality of multi-level cell memory chips by storing the sub-sequences of the selected candidate scrambled sequence across the plurality of multi-level memory chips. An encoding unit 6 may also be included to encode the selected scrambled sequence of data, before storing using an error correcting code (ECC). The scrambling operation may involve an XOR on the stored and scrambled data (figures 3 and 4) .

公开(公告)号：GB2527604A

公开(公告)日：2015-12-30

申请号：GB201411513

申请日：2014-06-27

Applicant: IBM

Inventor： MITTELHOLZER THOMAS ,  PAPANDREOU NIKOLAOS ,  PARNELL THOMAS ,  POZIDIS CHARALAMPOS

IPC: G11C11/56 ,  G06F11/10 ,  G11C13/00 ,  H03M13/00

Abstract: A method, apparatus (3,4 figures 1,10 and 11) and computer program implementation for encoding data for storage in multilevel (q-level) memory cells (2, figure 1) having q cell-levels. Input data words are encoded into respective codewords, each having N symbols with one of q symbol-values, via an encoding scheme adapted such that the q symbol-values have unequal multiplicities within at least some codewords (figure 3), and the multiplicity of each of the q symbol-values in every codeword is no less than p, where p is greater than or equal to two (2) and more preferably greater than or equal to three (3). A first type of encoding scheme uses recursive symbol-flipping to enforce the p-constraint, adding indicator symbols to indicate the flipped symbols. A second type of encoding scheme (figure 4) maps data words to codewords of a union of permutation codes, the initial vectors for these permutation codes being selected to enforce the p-constraint. The N q-ary symbols of each codeword are supplied for storage in respective cells of the multilevel memory 2. The multilevel memory cells may be flash or more preferably phase change memory cells. The apparatus and method is reported to improve the self adaptive detection techniques utilising estimate statistics in light of the effects of ageing and drifting of the memory cells.

公开(公告)号：DE112015005742T5

公开(公告)日：2017-11-30

申请号：DE112015005742

申请日：2015-12-15

Applicant: IBM

Inventor： PAPANDREOU NIKOLAOS ,  CAMP CHARLES JOHN ,  PARNELL THOMAS ,  POZIDIS CHARALAMPOS ,  MITTELHOLZER THOMAS

IPC: G06F12/16 ,  G06F3/06 ,  G06F12/00 ,  G06F12/04

Abstract: Ein Verfahren beinhaltet gemäß einer Ausführungsform Auswählen einer Kombination von komprimierten logischen Seiten von Daten aus einem Puffer, um einen Umfang von genutztem Raum in einem Fehlerkorrekturcode-Container auf den größtmöglichen Wert zu bringen. Das Verfahren enthält außerdem vorzugsweise Verarbeiten der Kombination von komprimierten logischen Seiten zum Erzeugen von Fehlerkorrekturcode-Daten. Das Verfahren kann des Weiteren beinhalten Schreiben der Daten, die der Kombination von komprimierten logischen Seiten entsprechen, und der zugehörigen Fehlerkorrekturcode-Daten in einen nichtflüchtigen Direktzugriffsspeicher. Weitere Systeme, Verfahren und Computerprogrammprodukte sind in zusätzlichen Ausführungsformen beschrieben.

公开(公告)号：GB2525430A

公开(公告)日：2015-10-28

申请号：GB201407279

申请日：2014-04-25

Applicant: IBM

Inventor： MITTELHOLZER THOMAS ,  PAPANDREOU NIKOLAOS ,  PARNELL THOMAS ,  POZIDIS CHARALAMPOS

IPC: H04L1/00 ,  H03M13/03

Abstract: Encoding data supplied to a data channel using a quarter product code CQ, having identical row and column codes and being reversible, whereby a codeword corresponds to a triangular sub-array of a square matrix confined between its diagonal and anti-diagonal. K input data symbols are stored for encoding. The K input data symbols are assigned to respective symbol locations in a notional square array, having n rows and n columns of symbol locations, to define a plurality of k-symbol words in respective rows of the array. The k-symbol words are encoded by encoding rows and columns of the array in dependence on a product code C having identical row and column codes, each being a reversible error-correction code of dimension k and length n=2n. This encoding is performed so as to define a codeword, having n2 code symbols corresponding to respective locations of said array, of a quarter product code CQ defined by CQ = { X − XT − (X − XT)F } where X is an (n by n)-symbol matrix defining a codeword of said product code C, XT is the transpose matrix of X, and (X − XT)F is a reflection of matrix (X − XT) in the anti-diagonal thereof. The n(n − 1) code symbols in said codeword of CQ which correspond to respective locations in a triangular sub-array confined between the diagonal and anti-diagonal of said array are then output to the data channel.