公开(公告)号：DE2041343A1

公开(公告)日：1971-03-18

申请号：DE2041343

申请日：1970-08-20

Applicant: IBM

Inventor： PHILLIP CASTRUCCI PAUL ,  ROGENE GATES HARLAN ,  ATHANASIUS HENLE ROBERT ,  DAVID PRICER WILBUR ,  MICHAEL MORTON ROBERT ,  WESTLEY MASON JOHN ,  DAVID NORTH WILLIAM

IPC: F22B21/06 ,  G11C17/06 ,  G11C17/14 ,  G11C17/16 ,  H01L23/525 ,  H01L27/00 ,  H01L27/102 ,  G11C17/00

Abstract: A read only memory having the capability of being written into once after manufacture. The cells of the memory are capable of being fused or permanently altered by directing a fusing current to the selected cells. The cell is a monolithic semiconductor device comprising a diode to be biased in a forward direction and a diode to be biased in the reverse direction structured so as to form back-to-back diodes. The reverse diode has a lower reverse breakdown voltage than the forward diode, and a metal connection, unconnected to any remaining circuit elements contacts the semiconductor device between diode junctions. The fusing current causes a metal-semiconductor alloy to form and short out the reverse diode.

公开(公告)号：DE1943300A1

公开(公告)日：1970-03-12

申请号：DE1943300

申请日：1969-08-26

Applicant: IBM

Inventor： DEWITT DAVID ,  ROGENE GATES HARLAN ,  PLATT ALAN

IPC: H01L21/761 ,  H01L29/08 ,  H01L7/36

Abstract: 1,263,127. Integrated circuits. INTERNATIONAL BUSINESS MACHINES CORP. 19 Aug., 1969 [5 Sept., 1968], No. 41319/69. Heading H1K. An individual isolation wall surrounding each component in an I.C. is produced by diffusing a first region of the opposite conductivity type into a substrate, depositing a first epitaxial layer of the same conductivity type as the substrate, diffusing a frame region of the opposite conductivity type through the layer to contact the first region, depositing a second epitaxial layer, and diffusing a second frame region through this layer to contact the first frame region. An N--type Si wafer (10) is thermally oxidized and the oxide photolithographically processed to provide openings into which an impurity is diffused to form P-type isolation regions (12), Fig. 2a (not shown). The surface is reoxidized and all the oxide removed and an N--type epitaxial layer (16) is deposited by the hydrogen reduction of SiCl 4 , Fig. 2b (not shown). The surface is oxide masked and impurities are diffused-in to form an annular P-type region (18), Fig. 2c (not shown), and an N + -type subcollector region 20, Fig. 2d (not shown). A second N--type epitaxial layer 22 is then deposited and a P-type annular region 28, and N + -type collector contact region 24, a P-type base region 26 and an N + -type emitter region 32 are formed by diffusion. During subsequent epitaxial growth and diffusion steps the impurities in P-type regions 12 and 18 and in N-type region 20 diffuse into the overlying layers so that the transistor is completely surrounded by a P-type isolation region and the region 24 contacts the sub-collector region 20. The N + -type collector contact region 24 and the emitter region 32 may be doped with phosphorus. The base region 26 may be formed simultaneously with the P-type isolation region 28. A low resistance cross-over may be provided in the wafer by forming a P-type "column" simultaneously with the three isolation region diffusions, conductive tracks in one direction passing over the "column" on an insulating layer while a track extending at right angles to the first direction is broken and has its ends in contact with spaced parts of the top of the "column" which completes the circuits, Fig. 3 (not shown).

公开(公告)号：DE1811389A1

公开(公告)日：1969-07-03

申请号：DE1811389

申请日：1968-11-28

Applicant: IBM

Inventor： ROGENE GATES HARLAN

IPC: H01L23/29 ,  H01L23/485 ,  H01L27/06 ,  H01L29/00 ,  H01L1/14