公开(公告)号：JP2000174435A

公开(公告)日：2000-06-23

申请号：JP30733399

申请日：1999-10-28

Applicant: IBM

Inventor： KENNETH FALLON ,  MAIGUERU A JIMAAZU ,  ROSS W KEITHLER ,  LAUFFER JOHN M ,  ROY H MAGNUSON ,  VOYA R MARKOVICH ,  AIRA MENISU ,  JIM P PAOLETTI ,  MAARIBESU PERINO ,  JOHN A WELSH ,  WILLIAM E WILSON

IPC: H05K3/42 ,  H05K1/05 ,  H05K3/00 ,  H05K3/10 ,  H05K3/44

Abstract: PROBLEM TO BE SOLVED: To obtain a circuit card, in which layers made of dielectric material for exposure type latent image formation are used on both opposing surfaces of a metal layer forming a power plane. SOLUTION: This method is provided for forming a printed circuit card. A metal layer 20 which functions as a power plane is sandwiched by a pair of layers 24 and 26 of a photoimageable material, capable of forming a latent with use of a light beam. Photoformed metal-filled vias 46 and photoformed plating through-hole 48 are in a photopatternable material. A signal circuit is formed on the two dielectric layers to be connected to the vias 46 and a through-hole 48. The board has a border 14 in its periphery, and the metal layer 20 has an end which is apart from an end of one 26 of the dielectric layers.

公开(公告)号：JP2001274288A

公开(公告)日：2001-10-05

申请号：JP2001017512

申请日：2001-01-25

Applicant: IBM

Inventor： TIMOTHY F GARDEN ,  TODD W DAVIS ,  ROSS W KEITHLER ,  ROBERT D SEBESUTA ,  DAVID B STONE ,  SHERRILL L TEITORAN-PAROMAKI

IPC: H01R33/76 ,  H01L23/12 ,  H01L23/498 ,  H01R4/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/42

Abstract: PROBLEM TO BE SOLVED: To improve the reliability and the manufacturing yield of the product of an integrated circuit chip carrier, by laying based on a new design method signal wirings which are routed from a semiconductor chip through a multilayer chip carrier, and by increasing the width of each signal wiring. SOLUTION: In a chip carrier 20 for mounting thereon a high density integrated circuit chip, while contact pads (i.e., micro-via holes) 22 whereby the chip and external circuits are interconnected electrically are provided by a first layout pattern, plated through holes (i.e., through via holes) 50, 52 are provided by a second layout pattern whose layout space is made larger than the one of the first layout pattern of the contact pads 22. Thereby, since the width of a wiring channel 51 provided between through holes 50, 52 in the chip carrier 20 is increased, the width of each signal trace 40 laid in the wiring channel 51 can be increased.