公开(公告)号：JP2001326470A

公开(公告)日：2001-11-22

申请号：JP2001087939

申请日：2001-03-26

Applicant: IBM

Inventor： DONS FRANCIS J JR ,  FARQUHAR DONALD S ,  FOUST ELIZABETH ,  ROBERT M JAPPU ,  JONES GERALD W ,  JOHN S KURIIJU ,  ROBERT D SEBESUTA ,  DAVID B STONE ,  JAMES R WILCOCKS

IPC: H05K1/02 ,  H01L23/12 ,  H01L23/14 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide an electronic package and a method of manufacturing the electronic package. SOLUTION: A package 10 is provided with a semiconductor chip 12 and a multilayer interconnection structure 18 having an allyl surface layer. The semiconductor chip 12 has a plurality of contact members 16 on one surface, and is connected with the inside of the multilayer interconnection structure 18 by using a plurality of solder connecting members 20. The multilayer interconnection structure 18 is constituted so as to electrically and interconnect circuits of a board 100 by using a plurality of other solder connecting members 47 and has a heat conduction layer 22 composed of material having a selected thickness and coefficient of thermal expansion with which solder connecting obstruction between a plurality of first conducting members and the semiconductor chip is prevented totally. The electronic package 10 includes dielectric material having effective tensile stress for ensuring sufficient compliancy with the multilayer interconnection structure 18 during operation. The allyl surface layer has characteristic capable of enduring thermal stress which is generated during heat cycle operation of the electronic package 10.

公开(公告)号：JP2001274288A

公开(公告)日：2001-10-05

申请号：JP2001017512

申请日：2001-01-25

Applicant: IBM

Inventor： TIMOTHY F GARDEN ,  TODD W DAVIS ,  ROSS W KEITHLER ,  ROBERT D SEBESUTA ,  DAVID B STONE ,  SHERRILL L TEITORAN-PAROMAKI

IPC: H01R33/76 ,  H01L23/12 ,  H01L23/498 ,  H01R4/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/42

Abstract: PROBLEM TO BE SOLVED: To improve the reliability and the manufacturing yield of the product of an integrated circuit chip carrier, by laying based on a new design method signal wirings which are routed from a semiconductor chip through a multilayer chip carrier, and by increasing the width of each signal wiring. SOLUTION: In a chip carrier 20 for mounting thereon a high density integrated circuit chip, while contact pads (i.e., micro-via holes) 22 whereby the chip and external circuits are interconnected electrically are provided by a first layout pattern, plated through holes (i.e., through via holes) 50, 52 are provided by a second layout pattern whose layout space is made larger than the one of the first layout pattern of the contact pads 22. Thereby, since the width of a wiring channel 51 provided between through holes 50, 52 in the chip carrier 20 is increased, the width of each signal trace 40 laid in the wiring channel 51 can be increased.

公开(公告)号：JP2001060644A

公开(公告)日：2001-03-06

申请号：JP2000192316

申请日：2000-06-27

Applicant: IBM

Inventor： JOHN S KURIIJU ,  ROBERT D SEBESUTA ,  DAVID B STONE ,  JAMES R WILCOCKS

IPC: H01L23/32 ,  H01L23/373 ,  H01L23/498 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide an electronic package mounted with an integrated circuit, and a method of manufacturing the electronic package. SOLUTION: An electronic package 10 is equipped with a semiconductor chip 12 and a multilayer interconnection structure 18. The semiconductor chip 2 is possessed of contact members 16, which are provided on its one surface and connected to the multilayered interconnection structure 18 with a solder connection members 20. The multilayer interconnection structure 18 is so structure as to electrically interconnect the semiconductor chip 12 to a circuit-shaped board (e.g., circuit board) 100 through other solder connection members and provided with a thermally conductive layer 22 of a material which has a prescribed thickness and thermal expansion coefficient, so as to nearly prevent obstruction of solder connections between the first conductive members and the semiconductor chip 12. The electronic package 10 is possessed of a dielectric material that has an effective tensile stress which ensures sufficient compliance of the multilayered interconnection structure in operation.

公开(公告)号：JPH10232631A

公开(公告)日：1998-09-02

申请号：JP3006798

申请日：1998-02-12

Applicant: IBM

Inventor： JEFFREY C VECTOR ,  MICHAEL A GAINES ,  MARK V PEARSON ,  DAVID B STONE ,  ANN M QUINN

IPC: G09F9/40 ,  G02F1/1333 ,  G02F1/1339

Abstract: PROBLEM TO BE SOLVED: To provide a display panel including display devices which are mutually positioned with accuracy and preferably sandwiched between light transmission plates made of glass by including a 1st light transmission plate, etc., having a 1st and a 2nd surface. SOLUTION: A sheet type joining material 25 is arranged in contact with the 1st surface 13 of the 1st light transmission plate 11, and the display devices 17 are arranged, one by one, accurately at specific positions having 1st surfaces 19 in contact with a 1st layer of the joining material 25. After all the display devices 17 are mounted at the specific positions, the 2nd layer of the sheet type joining material 45 is inserted between the display device and the surface 33 of a 1st a 2nd light transmission plate 31, and the 2nd light transmission plate 31 having the 1st surface 33 and 2nd surface 35 is joined with the 2nd surface 21 of the display device 17. The display device 17 is made nearly uniform in thickness so that it is easily joined with both the 1st and 2nd light transmission plates 11 and 31. The 2nd light transmission plate 31 is preferably of the same material (e.g. glass) and the same size with the plate 11.

公开(公告)号：GB2501853B

公开(公告)日：2017-02-08

申请号：GB201314831

申请日：2012-01-16

Applicant: IBM

Inventor： LUKE D LACROIX ,  MARK C H LAMOREY ,  STEVEN F OAKLAND ,  JANAK G PATEL ,  KERRY P PFARR ,  PETER SLOTA ,  DAVID B STONE

IPC: G01R31/02 ,  G01R31/28

公开(公告)号：MY124761A

公开(公告)日：2006-07-31

申请号：MYPI20002939

申请日：2000-06-28

Applicant: IBM

Inventor： JOHN S KRESGE ,  ROBERT D SEBESTA ,  DAVID B STONE ,  JAMES R WILCOX

IPC: H01L23/32 ,  H05K1/14 ,  H01L23/373 ,  H01L23/498 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46

Abstract: AN ELECTRONIC PACKAGE (10) AND METHOD OF MAKING THE ELECTRONIC PACKAGE IS PROVIDED.THE PACKAGE INCLUDES A SEMICONDUCTOR CHIP (12) AND AN MULTI-LAYERED INTERCONNECT STRUCTURE (18).THE SEMICONDUCTOR CHIP INCLUDES A PLURALITY OF CONTACT MEMBERS (16) ON ONE OF ITS SURFACES THAT ARE CONNECTED TO THE MULTI-LAYERED INTERCONNECT STRUCTURE BY A PLURALITY OF SOLDER CONNECTIONS (47).THE MULTI-LAYERED INTERCONNECT STRUCTURE IS ADAPTED FOR ELECTRICALLY INTERCONNECTING THE SEMICONDUCTOR CHIP TO A CIRCUITIZED SUBSTRATE (100) (EG.,CIRCUIT BOARD) WITH ANOTHER PLURALITY OF SOLDER CONNECTIONS (20) AND INCLUDES A THERMALLY CONDUCTIVE LAYER (22) BEING COMPRISED OF A MATERIAL HAVING A SELECTED THICKNESS AND COEFFICIENT OF THERMAL EXPANSION TO SUBSTANTIALLY PREVENT FAILURE OF THE SOLDER CONNECTIONS BETWEEN SAID FIRST PLURALITY OF ELECTRICALLY CONDUCTIVE MEMBERS AND THE SEMICONDUCTOR CHIP. THE ELECTRONIC PACKAGE FURTHER INCLUDES A DIELECTRIC MATERIAL HAVING AN EFFECTIVE MODULUS TO ASSURE SUFFICIENT COMPLIANCY OF THE MULTI-LAYERED INTERCONNECT STRUCTURE DURING OPERATION.(FIG 1)

公开(公告)号：SG87132A1

公开(公告)日：2002-03-19

申请号：SG200003659

申请日：2000-06-30

Applicant: IBM

Inventor： FRANCIS J DOWNES JR ,  DONALD S FARQUHAR ,  ELIZABETH FOSTER ,  ROBERT M JAPP ,  GERALD WALTER JONES ,  JOHN STEVEN KRESGE ,  ROBERT D SEBESTA ,  DAVID B STONE ,  JAMES R WILCOX

IPC: H01L23/32 ,  H01L21/48 ,  H01L23/373 ,  H01L23/498 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46 ,  H01L23/50 ,  H01L21/60

Abstract: A method of making a multi-layered interconnect structure. First and second electrically conductive members are formed on the first and second dielectric layers, respectively. The dielectric layer are formed on opposing surfaces of a thermally conductive layer. A first and second electrically conductive layer is formed within the first dielectric layer. The second electrically conductive layer includes shielded signal conductors and is positioned between the first electrically conductive layer and the thermally conductive layer. A plated through hole (PTH) formed through the interconnect structure is electrically connected to one of the first and second electrically conductive members and to one of the shielded signal conductors. A third dielectric layer, formed on the first dielectric layer and on portions of the first electrically conductive members, substantially overlies the PTH and includes a high density interconnect layer for providing an electrical path from an electronic device to the shielded signal conductors.

公开(公告)号：MY124540A

公开(公告)日：2006-06-30

申请号：MYPI20010429

申请日：2001-01-31

Applicant: IBM

Inventor： ROBERT D SEBESTA ,  TIMOTHY F CARDEN ,  TODD W DAVIES ,  ROSS W KEESLER ,  DAVID B STONE ,  CHERYL L TYTRAN-PALOMAKI

IPC: H01L23/12 ,  H01R33/76 ,  H01L23/498 ,  H01R4/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/42

Abstract: AN ORGANIC INTEGRATED CIRCUIT CHIP CARRIER (14) FOR HIGH DENSITY INTEGRATED CIRCUIT CHIP (12) ATTACH, WHEREIN THE CONTACT PADS (32) OR MICROVIAS (22) WHICH PROVIDE ELECTRICAL INTERCONNECTIONS TO EXTERNAL CIRCUITRY ARE LOCATED IN A FIRST ARRAY PATTERN, WHILE THE PLATED THROUGH HOLES OR THROUGH-VIAS (50,52) ARE LOCATED IN A SECOND ARRAY PATTERN. THIS ALLOWS UTILIZATION OF WIRING CHANNELS (51) WITHIN THE CHIP CARRIER IN WHICH SIGNAL WIRING TRACES (40) CAN BE ROUTED.

公开(公告)号：SG99347A1

公开(公告)日：2003-10-27

申请号：SG200100662

申请日：2001-02-06

Applicant: IBM

Inventor： TIMOTHY F CARDEN ,  TODD W DAVIES ,  ROSS WILLIAM KEESLER ,  ROBERT D SEBESTA ,  DAVID B STONE ,  CHERYL L TYTRAN-PALOMAKI

IPC: H01L23/12 ,  H01L23/498 ,  H01R33/76 ,  H01R4/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/42 ,  H05K3/40 ,  H05K3/36

Abstract: An organic integrated circuit chip carrier for high density integrated circuit chip attach, wherein the contact pads or microvias which provide electrical interconnections to external circuitry are located in a first array pattern, while the plated through holes or through-vias are located in a second array pattern. This allows utilization of wiring channels within the chip carrier in which signal wiring traces can be routed.

公开(公告)号：SG92715A1

公开(公告)日：2002-11-19

申请号：SG200003551

申请日：2000-06-24

Applicant: IBM

Inventor： JOHN STEVEN KRESGE ,  ROBERT D SEBESTA ,  DAVID B STONE ,  JAMES R WILCOX

IPC: H01L23/32 ,  H01L23/373 ,  H01L23/498 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46 ,  H05K7/14

Abstract: A method of making an electronic package. The method includes forming a semiconductor chip and an multi-layered interconnect structure. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The formed multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The method forms the electronic package to further include a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation.