公开(公告)号：JP2001326470A

公开(公告)日：2001-11-22

申请号：JP2001087939

申请日：2001-03-26

Applicant: IBM

Inventor： DONS FRANCIS J JR ,  FARQUHAR DONALD S ,  FOUST ELIZABETH ,  ROBERT M JAPPU ,  JONES GERALD W ,  JOHN S KURIIJU ,  ROBERT D SEBESUTA ,  DAVID B STONE ,  JAMES R WILCOCKS

IPC: H05K1/02 ,  H01L23/12 ,  H01L23/14 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide an electronic package and a method of manufacturing the electronic package. SOLUTION: A package 10 is provided with a semiconductor chip 12 and a multilayer interconnection structure 18 having an allyl surface layer. The semiconductor chip 12 has a plurality of contact members 16 on one surface, and is connected with the inside of the multilayer interconnection structure 18 by using a plurality of solder connecting members 20. The multilayer interconnection structure 18 is constituted so as to electrically and interconnect circuits of a board 100 by using a plurality of other solder connecting members 47 and has a heat conduction layer 22 composed of material having a selected thickness and coefficient of thermal expansion with which solder connecting obstruction between a plurality of first conducting members and the semiconductor chip is prevented totally. The electronic package 10 includes dielectric material having effective tensile stress for ensuring sufficient compliancy with the multilayer interconnection structure 18 during operation. The allyl surface layer has characteristic capable of enduring thermal stress which is generated during heat cycle operation of the electronic package 10.

公开(公告)号：JP2001274288A

公开(公告)日：2001-10-05

申请号：JP2001017512

申请日：2001-01-25

Applicant: IBM

Inventor： TIMOTHY F GARDEN ,  TODD W DAVIS ,  ROSS W KEITHLER ,  ROBERT D SEBESUTA ,  DAVID B STONE ,  SHERRILL L TEITORAN-PAROMAKI

IPC: H01R33/76 ,  H01L23/12 ,  H01L23/498 ,  H01R4/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/42

Abstract: PROBLEM TO BE SOLVED: To improve the reliability and the manufacturing yield of the product of an integrated circuit chip carrier, by laying based on a new design method signal wirings which are routed from a semiconductor chip through a multilayer chip carrier, and by increasing the width of each signal wiring. SOLUTION: In a chip carrier 20 for mounting thereon a high density integrated circuit chip, while contact pads (i.e., micro-via holes) 22 whereby the chip and external circuits are interconnected electrically are provided by a first layout pattern, plated through holes (i.e., through via holes) 50, 52 are provided by a second layout pattern whose layout space is made larger than the one of the first layout pattern of the contact pads 22. Thereby, since the width of a wiring channel 51 provided between through holes 50, 52 in the chip carrier 20 is increased, the width of each signal trace 40 laid in the wiring channel 51 can be increased.

公开(公告)号：JP2001060644A

公开(公告)日：2001-03-06

申请号：JP2000192316

申请日：2000-06-27

Applicant: IBM

Inventor： JOHN S KURIIJU ,  ROBERT D SEBESUTA ,  DAVID B STONE ,  JAMES R WILCOCKS

IPC: H01L23/32 ,  H01L23/373 ,  H01L23/498 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide an electronic package mounted with an integrated circuit, and a method of manufacturing the electronic package. SOLUTION: An electronic package 10 is equipped with a semiconductor chip 12 and a multilayer interconnection structure 18. The semiconductor chip 2 is possessed of contact members 16, which are provided on its one surface and connected to the multilayered interconnection structure 18 with a solder connection members 20. The multilayer interconnection structure 18 is so structure as to electrically interconnect the semiconductor chip 12 to a circuit-shaped board (e.g., circuit board) 100 through other solder connection members and provided with a thermally conductive layer 22 of a material which has a prescribed thickness and thermal expansion coefficient, so as to nearly prevent obstruction of solder connections between the first conductive members and the semiconductor chip 12. The electronic package 10 is possessed of a dielectric material that has an effective tensile stress which ensures sufficient compliance of the multilayered interconnection structure in operation.