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    Selection system for matrix displays requiring AC drive waveforms
    1.
    发明授权
    Selection system for matrix displays requiring AC drive waveforms 失效
    需要交流驱动波形的矩阵显示器选型系统

    公开(公告)号：US3911421A

    公开(公告)日：1975-10-07

    申请号：US42945973

    申请日：1973-12-28

    Applicant: IBM

    Inventor： ALT PAUL MATTHEW ,  PLESHKO PETER ,  SCHLIG EUGENE STEWART

    IPC: G09G3/36 ,  G02F1/133 ,  G09G3/20 ,  H04N3/12 ,  G02F1/18

    CPC classification number: H04N3/127

    Abstract: Alternating drive waveforms with zero direct voltage content for matrix or multiplexed displays are produced using low voltage, binary-level switching in the selection drive circuitry. Selection drive circuitry, and the breakdown voltage requirements thereof, are minimized by synthesizing the required high voltage waveforms applied to both the X and Y axes of display from lower amplitude components.

    Abstract translation: 在选择驱动电路中使用低电压二进制电平切换产生用于矩阵或多路复用显示器的零直流电压内容的交替驱动波形。 选择驱动电路及其击穿电压要求通过从低振幅分量合成施加到显示器的X和Y轴的所需高电压波形来最小化。

    4.
    发明专利
    未知

    公开(公告)号：DE1094305B

    公开(公告)日：1960-12-08

    申请号：DEI0017451

    申请日：1959-12-23

    Applicant: IBM

    Inventor： WALKER ROBERT MURRELL ,  SCHLIG EUGENE STEWART

    IPC: G11C11/44 ,  H01L39/00 ,  H03F19/00

    Abstract: 920,008. Superconductor circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 24, 1959 [Dec. 24, 1958], No. 43831/59. Class 40 (9). Two superconductive gate conductors 24, 26 are connected in parallel to a source 20 of constant current i2 and are self-biased by control coils 25, 27 connected in series with the conductors. The current i2 normally divides equally between the two branches as an increase in the current in one branch tends to drive the corresponding gate conductor more resistive. A signal current i1 in control coils 30, 31 aids the bias from coil 25 and opposes the bias from coil 27 to unbalance the circuit. There is a substantially linear relation between the signal current and the current in each branch. Two or more amplifiers may be connected in cascade. Specification 862,178 is referred to.

    5.
    发明专利
    未知

    公开(公告)号：DE69115866T2

    公开(公告)日：1996-07-11

    申请号：DE69115866

    申请日：1991-10-10

    Applicant: IBM

    Inventor： SCHLIG EUGENE STEWART ,  YAO YING LUH

    IPC: H04N1/04 ,  G06T1/00 ,  H04N1/48 ,  H04N9/04 ,  H04N1/46

    Abstract: An electronic imaging system develops red, green and blue images of a document in a single pass of the document through the system. The system includes an image sensor which has three time delay and integration (TDI) sensor arrays. Each sensor array is configured to have two optically masked rows of charge coupled devices (CCD's) for every row of CCD's that is used for imaging. The sensor arrays are arranged so that the first row of imaging CCD's on any two successive arrays are separated by a distance of an integer, K, times three times the height of a picture element (pel) of the image of the document that is projected onto the image sensor, plus or minus one pel height. The spectral component of the image of the document that is projected onto the image sensor is changed in sequence from red, to green, to blue. As the spectral component projected onto the image sensor is changed, the image of the document is scanned down the image sensor by a distance of one pel height. By this scheme, each line of pels in the document is imaged in each of the sensor arrays in a respectively different spectral component. A document may be imaged in all three colors in a single pass through the system without having dedicated filters for each of the separate sensor arrays.

    CHARGE COUPLED DEVICE AND CIRCUIT ARRANGEMENT FOR ITS OPERATION
    6.
    发明专利
    CHARGE COUPLED DEVICE AND CIRCUIT ARRANGEMENT FOR ITS OPERATION 未知

    公开(公告)号：DE3377316D1

    公开(公告)日：1988-08-11

    申请号：DE3377316

    申请日：1983-03-10

    Applicant: IBM

    Inventor： CHAMBERLAIN SAVVAS GEORGIOU ,  SCHLIG EUGENE STEWART

    IPC: G11C27/04 ,  H01L21/339 ,  H01L29/76 ,  H01L29/762 ,  H01L29/768 ,  H01L29/772 ,  H01L29/78

    Abstract: The output stage of a charge coupled device comprises a series of spaced electrodes (42, 44, 46, 48) formed on an insulating layer (18) and overlying the portion of a semiconductor layer (12) lying between a pair of enhanced conductivity regions (14, 16) formed in the layer (12). The first enhanced conductivity region (14) serves as the output region of the device and the last enhanced conductivity region (16) serves as a drain region. In operation, a reset pulse is applied to the first electrode (42) of the series and phase clock pulses are applied to intermediate electrodes (44, 46) of the series in synchronism with application of the clock pulses to the electrodes (22, 28) preceding the output region (14). A set (drain) pulse is applied to the last electrode (48) of the series and also to the last electrode (24) of the electrodes preceding the output region (14). Pulsing the electrode (24) immediately preceding the output region (14) serves to increase the change in potential of that region. Pulsing of the intermediate electrodes transfers the signal charge out of the output region (14) into an induced potential well before it is transferred to the drain region (16) by the set (drain) pulse applied to the last electrode (48). This extends the upper limit of the potential change of the output region (14) and also isolates the drain region (16) to obviate "charge sloshing".

    8.
    发明专利
    未知

    公开(公告)号：IT1149263B

    公开(公告)日：1986-12-03

    申请号：IT2596980

    申请日：1980-11-14

    Applicant: IBM

    Inventor： SCHLIG EUGENE STEWART

    IPC: G11C8/16 ,  G11C11/411 ,  G11C

    Abstract: A multiple access store having bipolar monolithic memory cells. Each cell includes a memory flip-flop comprised of cross-connected NPN transistors. A single concurrent read and write for each cell is achieved by a pair of accessing transistors, one accessing transistor of the pair connected at its base to the base of one of the flip-flop transistors and the other accessing transistor of the pair connected at its base to the base of the other of the flip-flop transistors. Each accessing transistor of an accessing transistor pair is connected at its collector to an associated bit/sense line. The emitter of each of the accessing transistors of an accessing transistor pair are connected together and the connected emitters are connected to a device that supplies a current supply to the emitters in response to a word signal. The emitters of the cross-connected flip-flop transistors are connected to an associated mode select line over which is applied a signal having a potential defining a write mode condition and a signal having a lower potential defining a read mode condition for the cell. Each pair of bit/sense lines and associated pair of accessing transistors that is added to each of the cells of a memory array may be operated to add an additional concurrent write of one word and a read of a different word for the array.

    10.
    发明专利
    未知

    公开(公告)号：DE1279747B

    公开(公告)日：1968-10-10

    申请号：DEJ0030614

    申请日：1966-04-14

    Applicant: IBM

    Inventor： FARBER ARNOLD STANLEY ,  SCHLIG EUGENE STEWART

    IPC: G11C11/38 ,  G11C11/411 ,  H03K3/286 ,  H03K3/288 ,  H03K3/315 ,  G11C11/34

    Abstract: 1,065,702. Semi-conductor data storage matrix. INTERNATIONAL BUSINESS MACHINES CORPORATION. Feb. 17, 1966 [April 19, 1965 (2)], No. 6937/66. Heading G4C. [Also in Division H3] The input of a bi-stable storage circuit is connected to the base of a transistor so as to be switched by base current which flows when a current is applied to the emitter and a pulse is applied to the collector to cause the transistor to saturate. The Figure shows a conventional cross-coupled bi-stable circuit Q4, Q5 for a storage matrix having a word driver line W and bit drive and read out lines A, B. If the circuit is in the state in which Q4 is conducting the base of a gating transistor Q2 is at - V volts whereas the base of Q3 is at earth potential. Accordingly when a word pulse cuts off driver transistor Q1 the current from R1 flows through Q3 to indicate in line B by a current pulse and in line A by the absence of a pulse, the state of the circuit. If, however, coincident with the pulse at W a negative pulse is applied at B, transistor Q3 will saturate and substantial emitter current will flow to the base of Q3 to render QS conducting and so change the state of the circuit. The original state will be similarly restored by coincident pulses at W and A instead of Q1 may be omitted if the word pulse W is applied at Ve (Fig. 5, not shown) and one of Q2, Q3 may be omitted if alternative reset arrangements are provided. In Fig. 6 (not shown) the bi-stable circuit is replaced by a tunnel diode (T), transistor Q2 having its base connected to the diode so that base current will change the state in one direction, the supply to the diode being derived from a line (c) to which reset pulses may be provided. The circuits may be arranged in a matrix (Fig. I, not shown) with word drivers (WD) connected to a line terminated in its characteristic impedance (Z) and the bit lines connected to bit drivers (BD) and sense amplifiers (SA).

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