公开(公告)号：JPH03253963A

公开(公告)日：1991-11-13

申请号：JP3753690

申请日：1990-02-20

Applicant: IBM

Inventor： OBA NOBUYUKI ,  SHIMIZU SHIGENORI

IPC: G06F12/08 ,  G06F15/16 ,  G06F15/177

Abstract: PURPOSE: To improve system performance by providing a means execution data consistency procedure to the data based on the comparing result and state information of a comparing means to reduce the traffic of a shared path. CONSTITUTION: A reference value register 6 stores a reference value in connection with the access count of a cache tag and a comparator 7 compares the access count of a cache tag specified by address information with the reference value of the reference value register 6 to supply the comparing result for a cache control part 3. In this case, with respect to data to which only one processor P frequently access, even though originally shared data, its copy is made to remain only in the cache C of the frequently accessing processor P and its copy within the other caches are invalidated. As the result of the, there is no copy in the other caches C after invalidating so that processing can be executed only within one's own cache C, thereby improving the performance of the bus of the cache to maximum.

公开(公告)号：JPH03217963A

公开(公告)日：1991-09-25

申请号：JP466890

申请日：1990-01-16

Applicant: IBM

Inventor： SHIMIZU SHIGENORI ,  OBARA MORIMIKI

IPC: G06F15/16 ,  G06F12/08 ,  G06F12/12 ,  G06F15/177

Abstract: PURPOSE: To improve the performance of a system by detecting a working set and eliminating an unrequired storage block. CONSTITUTION: Working set memories WSM1 -WSMn detect a limited memory space (the limited number of the storage blocks), that is the working set, and register the storage blocks belonging to it. Then, for memory access on a processor and a bus, whether or not the address is present in the registered working set is checked. Also, since the working set is changed in a long time, the storage block not used any more is eliminated from the working set memories WSM1 - WSMn .

公开(公告)号：JPH07200404A

公开(公告)日：1995-08-04

申请号：JP30368593

申请日：1993-12-03

Applicant: IBM

Inventor： SHIMIZU SHIGENORI

IPC: G06F12/08

Abstract: PURPOSE: To constitute a secondary cache which can operate with zero weight against a processor by using a DRAM and a system having a small area and small power consumption. CONSTITUTION: A data memory of a secondary cache is constituted by means of a DRAM and integrated on a single chip together with a control logic and a tag memory. At the same time, four words which are continuously accessed are interleaved in different rows and stored in the data memory. Thus, a DRAM access operation is attained at an apparently very high speed.

公开(公告)号：JPH0659974A

公开(公告)日：1994-03-04

申请号：JP17539892

申请日：1992-07-02

Applicant: IBM

Inventor： OBA NOBUYUKI ,  SHIMIZU SHIGENORI

IPC: G06F12/08

Abstract: PURPOSE: To efficiently execute cache consistency processing to be executed when an access occurs to a main memory from an input/output device. CONSTITUTION: A computer system consists of a processor 1, the cache memory 2 of this processor 1, a main memory 4, the input/output device 6 directly accessible to this main memory, an input/output controller 7, etc., so that the controller 7 may execute the processing of holding the coincidence of data between the cache memory 2 and the main memory 4 at the time of access to the main memory by the device 6. The controller 7 is provided with an address buffer 9 holding the cache line display of the address of the access of the last time so as not to execute the processing of holding coincidence except for first access, when access to the main memory 4 by the device 6 is consecutively occurs within the same address block.

公开(公告)号：DE69130583T2

公开(公告)日：1999-07-15

申请号：DE69130583

申请日：1991-02-11

Applicant: IBM

Inventor： OHBA NOBUYUKI ,  SHIMIZU SHIGENORI

IPC: G06F12/08 ,  G06F15/16 ,  G06F15/177

Abstract: Cache control system for a private cache in a multiprocessor data processing system comprising a plurality of processors each connected to a shared bus via similar private caches, the cache control system co-operating with similar cache control systems provided for other private caches in the data processing system, the cache control system comprising: a controller for monitoring signals on the shared bus and, when data shared between ones of the processors is modified in the cache, for performing one of two or more types of data consistency procedures for the shared data; and means for determining the relative likelihood of access to the shared data by the processor corresponding to the private cache and other processors in the system, the type of data consistency procedure performed by the controller being dependent on the results of the determination.

公开(公告)号：JPH11213659A

公开(公告)日：1999-08-06

申请号：JP1358698

申请日：1998-01-27

Applicant: IBM

Inventor： KATAYAMA YASUNAO ,  SHIMIZU SHIGENORI

IPC: G06F1/32 ,  G06F11/10 ,  G06F12/00 ,  G11C11/401 ,  G11C11/406 ,  G11C29/42

Abstract: PROBLEM TO BE SOLVED: To obtain an apparatus and a method in which the refresh interval of a memory device such as a dynamic random-access memory(DRAM) or the like which stores significant information and whose refresh is required in order to hold data is optimized in a sleep state. SOLUTION: An apparatus by which the refresh interval of a memory device 13 whose refresh is required is controlled in a sleep state is provided with an encoding circuit 3 which can be encoded to a code capable of correcting an error other than a double error, with a decoding circuit 5 which executes an error correction and a decoding operation and with a refresh-interval change circuit 7 which sets a refresh execution circuit 16 in such a way that data which is held in the memory device 13 after a shift to the sleep state and which is coded by the encoding circuit 3 is used, that the refresh execution circuit 15 in which an error row incapable of being corrected by the encoding circuit 5 does not exist, in which the number of error rows capable of being corrected is within a prescribed number, which executes the refresh of the memory device 13 can deal with the change of the refresh interval, that the change is executed until the refresh interval becomes longest and that the refresh of the memory device 13 is executed at a refresh interval after the finish of the change.

公开(公告)号：JPH04328653A

公开(公告)日：1992-11-17

申请号：JP11669391

申请日：1991-04-22

Applicant: IBM

Inventor： MURATA HIROKI ,  SHIMIZU SHIGENORI

IPC: G06F12/08 ,  G06F15/167

Abstract: PURPOSE: To improve the bandwidth of data transfer between a memory and a snoop cache by solving a bus bottleneck of a snoop cache type multiprocessor system. CONSTITUTION: A common bus connection is employed for an address/command bus 5 which requires bus snooping and a multiple data bus which is connected by an interconnection network 7 is used for a data bus which does not require bus snooping. The multiple data bus 7 has the order of snooping reflected on the order of data transfer enough to maintain the coincidence of data between caches.

公开(公告)号：JPH02186456A

公开(公告)日：1990-07-20

申请号：JP479989

申请日：1989-01-13

Applicant: IBM JAPAN

Inventor： MORIWAKI ATSUSHI ,  SHIMIZU SHIGENORI

IPC: G06F12/08 ,  G06F15/16 ,  G06F15/177

Abstract: PURPOSE:To flexibly switch by receiving a request signal and a write address to be sent, executing data operation corresponding to the type of its own data consistency maintaining procedure, which can be arbitrarily set, and returning data to a private cache. CONSTITUTION:When writing is executed to the 'shared' data of a private cache 2a, the request signal and update data are sent to a common bus 4 and after that, a response signal is waited. Controllers 3b and 3c of other caches 2b and 2c recognize the request signal and change data on the bus 4 respectively and execute determined operation to modification mode registers 8b and 8c. In the cache 2b side, the register 8b is positive and the controller 3b returns a negative signal as the response signal. On the other hand, in the cache 2c side, the register 8c is negative. Then, when the cache 2c obtains the data of the same address, the controller 3c updates these data by the update data and returns a positive signal as the response signal or otherwise, the controller 3c only returns the negative signal as the response signal. When the positive response signal is returned, the data are 'shared' in the cache 2a and when the negative response signal is returned, the data are 'occupied'.

公开(公告)号：DE69130580D1

公开(公告)日：1999-01-21

申请号：DE69130580

申请日：1991-01-04

Applicant: IBM

Inventor： SHIMIZU SHIGENORI ,  OHARA MORIYOSHI

IPC: G06F15/16 ,  G06F12/08 ,  G06F12/12 ,  G06F15/177

Abstract: A Cache memory system for a multiprocessor system having a multi cache configuration, the cache memory system performing data consistency procedures in different modes depending on whether the piece of data for which the procedure is to be performed belongs to a working set for the corresponding processor. In an embodiment, when a piece of data belongs to the working set an update mode is used, otherwise an invalidate mode is used. A mechanism is provided for updating the working set for the processor according to the frequency with which the data is accessed.

公开(公告)号：DE69130580T2

公开(公告)日：1999-07-15

申请号：DE69130580

申请日：1991-01-04

Applicant: IBM

Inventor： SHIMIZU SHIGENORI ,  OHARA MORIYOSHI

IPC: G06F15/16 ,  G06F12/08 ,  G06F12/12 ,  G06F15/177

Abstract: A Cache memory system for a multiprocessor system having a multi cache configuration, the cache memory system performing data consistency procedures in different modes depending on whether the piece of data for which the procedure is to be performed belongs to a working set for the corresponding processor. In an embodiment, when a piece of data belongs to the working set an update mode is used, otherwise an invalidate mode is used. A mechanism is provided for updating the working set for the processor according to the frequency with which the data is accessed.