公开(公告)号：US6410431B2

公开(公告)日：2002-06-25

申请号：US74653400

申请日：2000-12-19

Applicant: IBM

Inventor： BERTIN CLAUDE LOUIS ,  HOWELL WAYNE JOHN ,  TONTI WILLIAM R ,  ZALESINSKI JERZY MARIA

IPC: H01L23/13 ,  H01L23/367 ,  H01L23/48 ,  H01L21/44

CPC classification number: H01L23/13 ,  H01L23/3677 ,  H01L23/481 ,  H01L2223/6622 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2924/19104 ,  H01L2924/00014

Abstract: Through-chip conductors for low inductance chip-to-chip integration and off-chip connections in a semiconductor package is disclosed. A semiconductor device has active devices on the front surface, a first through-chip conductor having first electrical/physical characteristics passing from the front surface of the device to the back surface, a second through-chip conductor having second electrical/physical characteristics passing to the back surface, and an off-chip or chip-to-chip connector electrically connecting the active devices on the front surface to a different level of packaging.

Abstract translation: 公开了用于半导体封装中的低电感芯片到芯片集成和片外连接的芯片导体。 半导体器件在前表面上具有有源器件，具有从器件的前表面到后表面的第一电/物理特性的第一贯通芯片导体，具有第二电/物理特性的第二贯通芯片导体， 后表面，以及将前表面上的有源器件电连接到不同级别的封装的芯片外或芯片到芯片连接器。

公开(公告)号：EP1618609A4

公开(公告)日：2009-10-28

申请号：EP03816906

申请日：2003-04-30

Applicant: IBM

Inventor： TONTI WILLIAM R ,  BERRY WAYNE S ,  FIFIELD JOHN A ,  GUTHRIE WILLIAM H ,  KONTRA RICHARD S

IPC: H01L29/00 ,  H01L21/44 ,  H01L23/525

CPC classification number: G11C17/16 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1678764A4

公开(公告)日：2011-03-02

申请号：EP04817244

申请日：2004-10-04

Applicant: IBM

Inventor： ABADEER WAGDI W ,  FIFIELD JOHN A ,  TONTI WILLIAM R

IPC: H01L27/12 ,  H01L21/82 ,  H01L23/525 ,  H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

公开(公告)号：EP1581968A4

公开(公告)日：2007-04-18

申请号：EP02808339

申请日：2002-12-20

Applicant: IBM

Inventor： RANKIN JED H ,  ABADEER WAGDI W ,  BROWN JEFFREY S ,  CHATTY KIRAN V ,  TONTI WILLIAM R ,  GAUTHIER ROBERT J JR ,  FRIED DAVID M

IPC: H01L23/525 ,  H01L21/82 ,  H01L21/84 ,  H01L27/06 ,  H01L27/118 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/785 ,  H01L29/7854 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is described for fabricating and antifuse structure (100) integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material (11) is provided overlying an insulator (3) disposed on a substrate (10); an etching process exposes a plurality of corners (111-114) in the semiconducting material. The exposed corners are oxidized to form elongated tips (111t-114t) at the corners; the oxide (31) overlying the tips is removed. An oxide layer (51), such as a gate oxide, is then formed on the semiconducting material and overlying the corners; this layer has a reduced thickness at the corners. A layer of conducting material (60) is formed in contact with the oxide layer (51) at the corners, thereby forming a plurality of possible breakdown paths between the semiconducting material and the layer of conducting material through the oxide layer. Applying a voltage, such as a burn-in voltage, to the structure converts at least one of the breakdown paths to a conducting path (103, 280).

公开(公告)号：WO2005038869A3

公开(公告)日：2006-02-09

申请号：PCT/US2004032581

申请日：2004-10-04

Applicant: IBM ,  ABADEER WAGDI W ,  FIFIELD JOHN A ,  TONTI WILLIAM R

Inventor： ABADEER WAGDI W ,  FIFIELD JOHN A ,  TONTI WILLIAM R

IPC: H01L23/525 ,  H01L27/12 ,  H01L21/82 ,  H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit.

Abstract translation: 一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。 当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。 当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。 反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。 该电压差非常高，可以使用简单的感测电路容易地感测。

公开(公告)号：JP2007243176A

公开(公告)日：2007-09-20

申请号：JP2007039055

申请日：2007-02-20

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： TONTI WILLIAM R ,  MANDELMAN JACK A ,  HSU LOUIS LU-CHEN ,  WILLIAM P HOVIS ,  YANG CHIH-CHAO

IPC: H01L21/82 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an electrically programmable fuse structure for IC, and its manufacturing method. SOLUTION: This electrically programmable fuse has a first terminal part and second terminal part that are interconnected with fuse and elements. The first terminal part and second terminal part exist in different heights to the support surface of the fuse structure. The interconnecting fuse element connects the height difference between the height of the first terminal part and the second terminal part. While the first terminal part and second terminal part are oriented to be parallel with the support surface, the fuse element include a part oriented to be a right angle to the support surface, and also include at least one right-angled curvature portion that connects at least one of the first terminal element and second terminal element and the part of the fuse element oriented to be right angle. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为IC提供电可编程熔丝结构及其制造方法。 解决方案：该电可编程熔丝具有与熔丝和元件互连的第一端子部分和第二端子部分。 第一端子部分和第二端子部分与熔丝结构的支撑表面存在不同的高度。 互连保险丝元件连接第一端子部分和第二端子部分的高度之间的高度差。 当第一端子部分和第二端子部分被取向为与支撑表面平行时，熔丝元件包括定向成与支撑表面成直角的部分，并且还包括至少一个直角曲率部分，其连接在 第一端子元件和第二端子元件中的至少一个和熔丝元件的一部分被定向为直角。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JPH10241358A

公开(公告)日：1998-09-11

申请号：JP2699798

申请日：1998-02-09

Applicant: IBM

Inventor： HOUGHTON RUSSELL J ,  BERTIN CLAUDE L ,  FIFIELD JOHN A ,  MILLER CHRISTOPHER P ,  TONTI WILLIAM R

IPC: G11C11/402 ,  G11C11/403 ,  G11C11/405

Abstract: PROBLEM TO BE SOLVED: To prevent read-out disturbance from an unselected cell by reading out a written word value stored on a storage node by means of a read transistor via a diode between bit lines. SOLUTION: When a write transistor Tw0 in a gain cell 20 is operated by a write-in word line WLW0, a value of a write-in bit line BLW0 is stored on the storage node SN0. When a read-out word line WLR0 is enabled to work, the read transistor Tr0 to be connected with the storage node SN0 in this case is connected via the diode D0 to a read-out bit line BLR0, so as to read out the stored value. The diode D0 is capable of preventing conductivity in the reverse direction of the read transistor Tr0, thus preventing disturbance from another cell, and also decreasing capacitance of the bit line. The same is the case with the other memory cells.

公开(公告)号：JP2007158342A

公开(公告)日：2007-06-21

申请号：JP2006326844

申请日：2006-12-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ABADEER WAGDI W ,  HAUSER MICHAEL J ,  ADKISSON JAMES W ,  RANKIN JED H ,  GAUTHIER ROBERT J JR ,  CHATTY KIRAN V ,  JEFFREY SCOTT BROWN ,  TONTI WILLIAM R

IPC: H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/14 ,  H01L31/12

CPC classification number: H01L23/5256 ,  H01L23/525 ,  H01L27/14609 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method of executing an electrical function such as a fusing operation by activation through a chip-embedded photodiode through spectrally selected external light activation, a corresponding structure, and a corresponding circuit. SOLUTION: In conjunction with additional circuit elements to an integrated circuit, incident light with specific intensity/wave length characteristics performs the implementation of repairs. More specifically, failing circuit elements are replaced with redundant ones for yield and/or reliability, and, after a packaged chip is placed in the system, the incident light makes an ESD protection device be disconnected from input pad. No additional pins on the package are necessary. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种通过光谱选择的外部光激活，对应的结构和相应的电路来通过芯片嵌入式光电二极管的激活来执行诸如定影操作之类的电功能的方法。

解决方案：结合集成电路的附加电路元件，具有特定强度/波长特性的入射光执行维修。 更具体地，用于产生和/或可靠性的冗余电路元件被替换，并且在将封装芯片放置在系统中之后，入射光使得ESD保护装置与输入焊盘断开连接。 不需要额外的引脚。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007158330A

公开(公告)日：2007-06-21

申请号：JP2006317786

申请日：2006-11-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MANDELMAN JACK ALLAN ,  LOUIS LU-CHEN HSU ,  YANG CHIH-CHAO ,  TONTI WILLIAM R

IPC: H01L21/82 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L29/786

CPC classification number: H01L23/5256 ,  H01L21/268 ,  H01L21/84 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure including at least one e-fuse, and a manufacturing method which is easily integrated with standard semiconductor technologies, thus minimizing implementation costs. SOLUTION: A semiconductor structure includes at least one e-fuse embedded in a trench that is located in a semiconductor substrate (a bulk or semiconductor-on-insulator substrate). According to the present invention, the e-fuse is in electrical contact with a dopant region that is located in the semiconductor substrate. The present invention also provides a method of manufacturing the semiconductor structure in which the embedded e-fuse and trench isolation regions are formed almost at the same time. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供包括至少一个电熔丝的半导体结构和容易与标准半导体技术集成的制造方法，从而最小化实施成本。 解决方案：半导体结构包括嵌入在半导体衬底（主体或绝缘体上半导体衬底）上的沟槽中的至少一个电熔丝。 根据本发明，电熔丝与位于半导体衬底中的掺杂区电接触。 本发明还提供了一种制造半导体结构的方法，其中嵌入式电熔丝和沟槽隔离区几乎同时形成。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2005197743A

公开(公告)日：2005-07-21

申请号：JP2005000921

申请日：2005-01-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CASEY JON A ,  FERRANTE WILLIAM J ,  KIEWRA EDWARD W ,  RADENS CARL J ,  TONTI WILLIAM R

IPC: H01L21/28 ,  G01K7/22 ,  H01C7/00 ,  H01L21/3205 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04

CPC classification number: H01L21/76895 ,  G01K7/226 ,  H01C7/006 ,  H01L21/76224 ,  H01L21/76838

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for forming a thermistor.
SOLUTION: An isolation region is formed in a substrate including at least an upper side layer of a single crystal semiconductor. A salicide precursor layer is formed on the isolation region and the upper side layer. Then, reaction of the salicide precursor and the upper side layer is performed and a salicide which is self-aligned to the upper side layer is formed. Finally, no reaction portion of the salicide precursor is removed, while preserving the portion of the salicide precursor on the isolation region as the main body of the thermistor. In alternative method, an integrated circuit thermistor is formed from a thermistor material region in an embossed region of interlayer dielectric (ILD).
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于形成热敏电阻的结构和方法。 解决方案：在至少包含单晶半导体的上侧层的衬底中形成隔离区。 在隔离区域和上侧层上形成自对准硅化物前体层。 然后，进行自对准硅化物前体与上侧层的反应，形成与上侧层自对准的自对准硅化物。 最后，除去自杀化合物前体的反应部分，同时保留作为热敏电阻的主体的隔离区上的部分自杀化合物前体。 在替代方法中，集成电路热敏电阻由层间电介质（ILD）的压花区域中的热敏电阻材料区域形成。 版权所有（C）2005，JPO＆NCIPI