公开(公告)号：WO2012168097A4

公开(公告)日：2013-01-31

申请号：PCT/EP2012059855

申请日：2012-05-25

Applicant: IBM ,  IBM UK ,  GAINEY JR CHARLES ,  OAKES KENNETH JAMES ,  MATHIAS THOMAS BRIAN ,  SZWED PETER KENNETH ,  DRIEVER PETER DANA ,  SUTTON PETER GRIMM ,  YUDENFRIEND HARRY ,  TZORTZATOS ELPIDA ,  GLASSEN STEVEN GARDNER

Inventor： GAINEY JR CHARLES ,  OAKES KENNETH JAMES ,  MATHIAS THOMAS BRIAN ,  SZWED PETER KENNETH ,  DRIEVER PETER DANA ,  SUTTON PETER GRIMM ,  YUDENFRIEND HARRY ,  TZORTZATOS ELPIDA ,  GLASSEN STEVEN GARDNER

IPC: G06F9/50

CPC classification number: G06F12/0646 ,  G06F9/5011 ,  G06F9/5016

Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

Abstract translation: 提供存储类存储器的抽象，其隐藏来自程序的存储类存储器的实现的细节，并且提供用于执行某些动作的标准通道编程接口，例如控制主存储和存储类存储器之间的数据移动或管理 存储类内存

公开(公告)号：EP2601582A4

公开(公告)日：2013-06-12

申请号：EP12796711

申请日：2012-05-22

Applicant: IBM

Inventor： GAINEY JR CHARLES ,  OAKES KENNETH JAMES ,  MATHIAS THOMAS BRIAN ,  SZWED PETER KENNETH ,  DRIEVER PETER DANA ,  SUTTON PETER GRIMM ,  YUDENFRIEND HARRY ,  TZORTZATOS ELPIDA ,  GLASSEN STEVEN GARDNER

IPC: G06F12/08

CPC classification number: G06F3/0605 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0632 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0688 ,  G06F9/3004 ,  G06F9/30076 ,  G06F12/0246 ,  G06F12/0646 ,  G06F13/14 ,  G06F2212/214 ,  G06F2212/7202

公开(公告)号：GB2506073A

公开(公告)日：2014-03-19

申请号：GB201400048

申请日：2012-05-25

Applicant: IBM

Inventor： GAINEY CHARLES JR ,  OAKES KENNETH JAMES ,  MATHIAS THOMAS BRIAN ,  SZWED PETER KENNETH ,  DRIEVER PETER DANA ,  SUTTON PETER GRIMM ,  YUDENFRIEND HARRY ,  TZORTZATOS ELPIDA ,  GLASSEN STEVEN GARDNER

IPC: G06F13/38

Abstract: Provided is a method of executing an instruction to execute a Store Storage Class Memory Information command in a computing environment comprising main storage and storage class memory, the method comprising: obtaining by an input/output (I/O) subsystem a request block, the request block comprising a command code indicating the Store Storage Class Memory Information command; based on the command code, obtaining by the I/O subsystem information relating to the storage class memory; and storing the information in a response block, the response block configured to include a header area and a storage class memory address list of one or more entries representing one or more storage class memory increments that occupy one or more ranges of storage class memory addresses, and wherein the storing the information comprises storing header information in the header area and storing the one or more entries in the response block, wherein the header area includes parameters about the list of one or more entries including an indication of a size of storage class memory increments.

公开(公告)号：AU2022287210A1

公开(公告)日：2023-11-02

申请号：AU2022287210

申请日：2022-05-31

Applicant: IBM

Inventor： GIAMEI BRUCE ,  SLEGEL TIMOTHY ,  BORNTRAEGER CHRISTIAN ,  OSISEK DAMIAN ,  HELLER LISA ,  GAERTNER UTE ,  YOST CHRISTINE ,  TZORTZATOS ELPIDA

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F12/14

Abstract: An instruction is provided to perform a reset address translation protection operation when executed. Executing the instruction includes determining, by a processor, that an address translation protection bit in a specified translation table entry associated with a storage block is to be reset. Based on determining that the address translation protection bit is to be reset, executing the instruction includes resetting the address translation protection bit to deactivate write protection for the storage block. The resetting is absent waiting for an action by one or more other processors of the computing environment.

公开(公告)号：SG194599A1

公开(公告)日：2013-12-30

申请号：SG2013078829

申请日：2012-05-22

Applicant: IBM

Inventor： GAINEY JR CHARLES ,  OAKES KENNETH JAMES ,  MATHIAS THOMAS BRIAN ,  SZWED PETER KENNETH ,  DRIEVER PETER DANA ,  SUTTON PETER GRIMM ,  YUDENFRIEND HARRY ,  TZORTZATOS ELPIDA ,  GLASSEN STEVEN GARDNER

Abstract: ion for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

公开(公告)号：AU2012265964A1

公开(公告)日：2013-05-02

申请号：AU2012265964

申请日：2012-05-22

Applicant: IBM

Inventor： GAINEY JR CHARLES ,  OAKES KENNETH JAMES ,  MATHIAS THOMAS BRIAN ,  SZWED PETER KENNETH ,  DRIEVER PETER DANA ,  SUTTON PETER GRIMM ,  YUDENFRIEND HARRY ,  TZORTZATOS ELPIDA ,  GLASSEN STEVEN GARDNER

IPC: G06F13/00

Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

公开(公告)号：CA2819213A1

公开(公告)日：2012-12-13

申请号：CA2819213

申请日：2012-05-22

Applicant: IBM

Inventor： GAINEY CHARLES JR ,  OAKES KENNETH JAMES ,  MATHIAS THOMAS BRIAN ,  SZWED PETER KENNETH ,  DRIEVER PETER DANA ,  SUTTON PETER GRIMM ,  YUDENFRIEND HARRY ,  TZORTZATOS ELPIDA ,  GLASSEN STEVEN GARDNER

IPC: G06F13/00

Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

公开(公告)号：AU2022287210B2

公开(公告)日：2024-12-12

申请号：AU2022287210

申请日：2022-05-31

Applicant: IBM

Inventor： GIAMEI BRUCE ,  SLEGEL TIMOTHY ,  BORNTRAEGER CHRISTIAN ,  OSISEK DAMIAN ,  HELLER LISA ,  GAERTNER UTE ,  YOST CHRISTINE ,  TZORTZATOS ELPIDA

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F12/14

Abstract: An instruction is provided to perform a reset address translation protection operation when executed. Executing the instruction includes determining, by a processor, that an address translation protection bit in a specified translation table entry associated with a storage block is to be reset. Based on determining that the address translation protection bit is to be reset, executing the instruction includes resetting the address translation protection bit to deactivate write protection for the storage block. The resetting is absent waiting for an action by one or more other processors of the computing environment.

公开(公告)号：MX2023013910A

公开(公告)日：2023-12-08

申请号：MX2023013910

申请日：2022-05-31

Applicant: IBM

Inventor： HELLER LISA ,  SLEGEL TIMOTHY ,  BORNTRAEGER CHRISTIAN ,  GIAMEI BRUCE ,  OSISEK DAMIAN ,  GAERTNER UTE ,  YOST CHRISTINE ,  TZORTZATOS ELPIDA

IPC: G06F12/1009 ,  G06F12/02 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/14

Abstract: Se proporciona una instrucción para llevar a cabo una operación de reinicio de protección de traducción de dirección cuando se ejecuta. Ejecutar la instrucción incluye determinar, por medio de un procesador, que se va a reiniciar un bit de protección de traducción de dirección en una entrada de tabla de traducción especificada asociada con un bloque de almacenamiento. Con base en la determinación de que se va a reiniciar el bit de protección de traducción de dirección, ejecutar la instrucción incluye reiniciar el bit de protección de traducción de dirección para desactivar la protección contra escritura para el bloque de almacenamiento. El reinicio no espera una acción por uno o más de otros procesadores del entorno de cómputo.

公开(公告)号：DE112018004636B4

公开(公告)日：2021-12-30

申请号：DE112018004636

申请日：2018-11-08

Applicant: IBM

Inventor： MATSAKIS NICHOLAS ,  WALTERS CRAIG ,  BARTIK JANE ,  SHUM CHUNG-LUNG ,  TZORTZATOS ELPIDA

IPC: G06F9/46 ,  G06F12/08

Abstract: Eine gemeinsam genutzten Cachezeile wird von mehreren Prozessoren einer Datenverarbeitungsumgebung gleichzeitig geändert. Die gleichzeitige Änderung wird mindestens beruhend darauf durchgeführt, dass eine oder mehrere architekturdefinierte Anweisungen („Fetch due to Non-Coherent Store“-Anweisungen) empfangen werden, die es mehreren Prozessoren gestatten, die gemeinsam genutzte Cachezeile gleichzeitig zu aktualisieren, ohne eine Sperre zu erhalten oder über eine exklusive Eigentümerschaft der Daten zu verfügen.