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公开(公告)号:SG11202102996YA
公开(公告)日:2021-04-29
申请号:SG11202102996Y
申请日:2019-11-05
Applicant: IBM
Inventor: GIAMEI BRUCE , RECKTENWALD MARTIN , SCHMIDT DONALD , SLEGEL TIMOTHY , PURANIK ADITYA , FARRELL MARK , JACOBI CHRISTIAN , BRADBURY JONATHAN , ZOELLIN CHRISTIAN
IPC: G06F9/30
Abstract: A Sort Lists instruction is provided to perform a sort and/or a merge operation. The instruction is an architected machine instruction of an instruction set architecture and is executed by a general-purpose processor of the computing environment. The executing includes sorting a plurality of input lists to obtain one or more sorted output lists, which are output.
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公开(公告)号:BR112023021648A2
公开(公告)日:2023-12-26
申请号:BR112023021648
申请日:2022-05-31
Applicant: IBM
Inventor: GIAMEI BRUCE , BORNTRAEGER CHRISTIAN , YOST CHRISTINE , OSISEK DAMIAN , TZORTZATOS ELPIDA , HELLER LISA , SLEGEL TIMOTHY , GAERTNER UTE
IPC: G06F12/14 , G06F12/1009 , G06F12/1027
Abstract: instrução de redefinição de proteção de tradução de endereço dinâmico. uma instrução é fornecida para executar uma operação de redefinição de proteção de tradução de endereço quando executada. a execução da instrução inclui determinar, por um processador, que um bit de proteção de tradução de endereço em uma entrada de tabela de tradução especificada associada a um bloco de armazenamento deve ser redefinido. com base na determinação de que o bit de proteção de tradução de endereço deve ser redefinido, a execução da instrução inclui a redefinição do bit de proteção de tradução de endereço para desativar a proteção contra gravação para o bloco de armazenamento. a redefinição está ausente, aguardando uma ação de um ou mais outros processadores do ambiente de computação.
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公开(公告)号:ES2929826T3
公开(公告)日:2022-12-01
申请号:ES19798279
申请日:2019-11-05
Applicant: IBM
Inventor: GIAMEI BRUCE , RECKTENWALD MARTIN , SCHMIDT DONALD , SLEGEL TIMOTHY , PURANIK ADITYA , FARRELL MARK , JACOBI CHRISTIAN , BRADBURY JONATHAN , ZOELLIN CHRISTIAN
IPC: G06F9/30
Abstract: Se proporciona una instrucción de clasificación de listas para realizar una operación de clasificación y/o combinación. La instrucción es una instrucción de máquina con arquitectura de una arquitectura de conjunto de instrucciones y es ejecutada por un procesador de propósito general del entorno informático. La ejecución incluye ordenar una pluralidad de listas de entrada para obtener una o más listas de salida ordenadas, que son salida. (Traducción automática con Google Translate, sin valor legal)
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公开(公告)号:ES2993311T3
公开(公告)日:2024-12-27
申请号:ES20701987
申请日:2020-01-23
Applicant: IBM
Inventor: GIAMEI BRUCE , SOFIA ANTHONY , KLEIN MATTHIAS , WEISHAUPT SIMON , FARRELL MARK , SLEGEL TIMOTHY , MISHRA ASHUTOSH , JACOBI CHRISTIAN
IPC: G06F9/30
Abstract: Se obtiene una instrucción para realizar una función de una pluralidad de funciones. La instrucción es una instrucción diseñada de manera única de una arquitectura de conjunto de instrucciones que cumple con un estándar de la industria para la compresión. La instrucción se ejecuta, y la ejecución incluye realizar la función especificada por la instrucción. La ejecución incluye, en función de que la función sea una función de compresión o una función de descompresión, transformar el estado de los datos de entrada entre una forma no comprimida de los datos de entrada y una forma comprimida de los datos de entrada para proporcionar un estado transformado de acceso a los datos. Durante la ejecución de la función, se accede al historial relacionado con la función. El historial se va a utilizar para transformar el estado de los datos de entrada entre la forma no comprimida y la forma comprimida. (Traducción automática con Google Translate, sin valor legal)
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公开(公告)号:AU2022287210B2
公开(公告)日:2024-12-12
申请号:AU2022287210
申请日:2022-05-31
Applicant: IBM
Inventor: GIAMEI BRUCE , SLEGEL TIMOTHY , BORNTRAEGER CHRISTIAN , OSISEK DAMIAN , HELLER LISA , GAERTNER UTE , YOST CHRISTINE , TZORTZATOS ELPIDA
IPC: G06F12/1009 , G06F12/1027 , G06F12/14
Abstract: An instruction is provided to perform a reset address translation protection operation when executed. Executing the instruction includes determining, by a processor, that an address translation protection bit in a specified translation table entry associated with a storage block is to be reset. Based on determining that the address translation protection bit is to be reset, executing the instruction includes resetting the address translation protection bit to deactivate write protection for the storage block. The resetting is absent waiting for an action by one or more other processors of the computing environment.
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公开(公告)号:MX2023013910A
公开(公告)日:2023-12-08
申请号:MX2023013910
申请日:2022-05-31
Applicant: IBM
Inventor: HELLER LISA , SLEGEL TIMOTHY , BORNTRAEGER CHRISTIAN , GIAMEI BRUCE , OSISEK DAMIAN , GAERTNER UTE , YOST CHRISTINE , TZORTZATOS ELPIDA
IPC: G06F12/1009 , G06F12/02 , G06F12/0891 , G06F12/1027 , G06F12/14
Abstract: Se proporciona una instrucción para llevar a cabo una operación de reinicio de protección de traducción de dirección cuando se ejecuta. Ejecutar la instrucción incluye determinar, por medio de un procesador, que se va a reiniciar un bit de protección de traducción de dirección en una entrada de tabla de traducción especificada asociada con un bloque de almacenamiento. Con base en la determinación de que se va a reiniciar el bit de protección de traducción de dirección, ejecutar la instrucción incluye reiniciar el bit de protección de traducción de dirección para desactivar la protección contra escritura para el bloque de almacenamiento. El reinicio no espera una acción por uno o más de otros procesadores del entorno de cómputo.
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公开(公告)号:HUE069005T2
公开(公告)日:2025-02-28
申请号:HUE20701987
申请日:2020-01-23
Applicant: IBM
Inventor: GIAMEI BRUCE , SOFIA ANTHONY , KLEIN MATTHIAS , WEISHAUPT SIMON , FARRELL MARK , SLEGEL TIMOTHY , MISHRA ASHUTOSH , JACOBI CHRISTIAN
IPC: G06F9/30
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公开(公告)号:AU2022287210A1
公开(公告)日:2023-11-02
申请号:AU2022287210
申请日:2022-05-31
Applicant: IBM
Inventor: GIAMEI BRUCE , SLEGEL TIMOTHY , BORNTRAEGER CHRISTIAN , OSISEK DAMIAN , HELLER LISA , GAERTNER UTE , YOST CHRISTINE , TZORTZATOS ELPIDA
IPC: G06F12/1009 , G06F12/1027 , G06F12/14
Abstract: An instruction is provided to perform a reset address translation protection operation when executed. Executing the instruction includes determining, by a processor, that an address translation protection bit in a specified translation table entry associated with a storage block is to be reset. Based on determining that the address translation protection bit is to be reset, executing the instruction includes resetting the address translation protection bit to deactivate write protection for the storage block. The resetting is absent waiting for an action by one or more other processors of the computing environment.
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公开(公告)号:SG11202105494SA
公开(公告)日:2021-06-29
申请号:SG11202105494S
申请日:2020-02-20
Applicant: IBM
Inventor: KLEIN MATTHIAS , GIAMEI BRUCE , SOFIA ANTHONY , FARRELL MARK , SWANEY SCOTT , SLEGEL TIMOTHY
IPC: G06F9/455
Abstract: A system is provided and includes a plurality of machines. The plurality of machines includes a first generation machine and a second generation machine. Each of the plurality of machines includes a machine version. The first generation machine executes a first virtual machine and a virtual architecture level. The second generation machine executes a second virtual machine and the virtual architecture level. The virtual architecture level provides a compatibility level for a complex interruptible instruction to the first and second virtual machines. The compatibility level is architected for a lowest common denominator machine version across the plurality of machines. The compatibility level includes a lowest common denominator indicator identifying the lowest common denominator machine version.
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公开(公告)号:CA3217151A1
公开(公告)日:2022-12-08
申请号:CA3217151
申请日:2022-05-31
Applicant: IBM
Inventor: GIAMEI BRUCE , SLEGEL TIMOTHY , BORNTRAEGER CHRISTIAN , OSISEK DAMIAN , HELLER LISA , GAERTNER UTE , YOST CHRISTINE , TZORTZATOS ELPIDA
IPC: G06F12/1009 , G06F12/1027
Abstract: An instruction is provided to perform a reset address translation protection operation when executed. Executing the instruction includes determining, by a processor, that an address translation protection bit in a specified translation table entry associated with a storage block is to be reset. Based on determining that the address translation protection bit is to be reset, executing the instruction includes resetting the address translation protection bit to deactivate write protection for the storage block. The resetting is absent waiting for an action by one or more other processors of the computing environment.
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