公开(公告)号：JP2000174441A

公开(公告)日：2000-06-23

申请号：JP30748199

申请日：1999-10-28

Applicant: IBM

Inventor： LAUFFER JOHN M ,  ROY H MAGNUSON ,  VOYA R MARKOVICH ,  JOHN A WELSH

IPC: H05K3/00 ,  H05K3/42 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To form a chip carrier having two voltage faces and at least two signal faces by exposing a first layer made of dielectric material attached to a first metal layer to form openings which pass through the first layer. SOLUTION: A first layer 10 made of dielectric material is attached to a first metal layer 12 and then the first layer 10 is exposed to form openings which pass through the first layer 10. Then, a second metal layer 16 is attached to the first layer 10 and holes larger than corresponding opening patterns of the first layer 10 are formed by etching in the first and the second metal layer 12, 16 in correspondence to each opening pattern and then an exposure pattern on the first layer 10 is developed. The openings formed in the first and the second metal layer are larger than those of the first layer 10. Then, a second and a third layer 32, 34 which are capable of light image formation are attached to the first and the second metal layer 12, 16 respectively and then are formed into light patterns and developed to form openings corresponding to each hole of the first layer 10 in the second and the third layer 32, 34. Then, the first and the second metal layer 12, 16 are formed with holes which are terminated at the metal layer in the lower layer. Parts of the surfaces of the second and the third dielectric material are exposed and holes are filled with plating or metal.

公开(公告)号：JP2000294927A

公开(公告)日：2000-10-20

申请号：JP2000092241

申请日：2000-03-29

Applicant: IBM

Inventor： BERND K APPELT ,  JOHN M LAUFER ,  VOYA R MARKOVICH ,  MEMIS IRVING ,  DAVID J RUSSELL

IPC: H05K3/28 ,  H05K3/00 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a method, in which a multilayer circuit board is formed on a board which comprises a first-level circuit pattern on at least one face. SOLUTION: This manufacturing method for a circuit board comprises a process 80, in which a dielectric capable of permanent imaging is formed as to cover a first-level circuit pattern. The manufacturing method contains a process 82, in which the dielectric capable of permanent imaging is exposed to radiation, process 84 in which a conductive metal layer is laminated on the dielectric, a process 86 in which a hole is formed in the conductive metal layer and the dielectric by a laser, a plasma ablation operation or a mechanical drilling operation, a process 8 in which a second-level circuit pattern is formed in which the hole is filled with a conductive material and in which the first-level circuit pattern and the second-level circuit pattern are connected electrically.

公开(公告)号：JP2000188473A

公开(公告)日：2000-07-04

申请号：JP24210499

申请日：1999-08-27

Applicant: IBM

Inventor： LAUFFER JOHN M ,  VOYA R MARKOVICH ,  CHERIRU L PAROMAKI ,  WILLIAM E WILSON

IPC: H05K3/42 ,  C08L63/00 ,  C08L101/12 ,  C09D5/34 ,  C09D163/00 ,  H01B3/40 ,  H05K1/11 ,  H05K3/00 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a method in which an opening in a substrate such as a through hole or the like is filled. SOLUTION: An epoxy resin-based dielectric film 16 which covers an opening 14 is arranged on a substrate 12 which comprises the opening 14. The dielectric film 16 is made to reflow so as to flow into the opening 14. A continuous dielectric which is extended into the opening 14 from the dielectric film 16 is formed. When a via 18 is formed after the opening 14 is filled, light is image-formed on the dielectric film 16, the via 18 is metallized, and a circuit structure 24 is formed. It is preferable that the dielectric film 16 contains 0 to 50% of inorganic fine particles, 50 to 100% of an epoxy resin and a cation photoinhibitor of 0.1 to 15 pts.wt. in terms of the total weight of the resin are contained.

公开(公告)号：JP2000174435A

公开(公告)日：2000-06-23

申请号：JP30733399

申请日：1999-10-28

Applicant: IBM

Inventor： KENNETH FALLON ,  MAIGUERU A JIMAAZU ,  ROSS W KEITHLER ,  LAUFFER JOHN M ,  ROY H MAGNUSON ,  VOYA R MARKOVICH ,  AIRA MENISU ,  JIM P PAOLETTI ,  MAARIBESU PERINO ,  JOHN A WELSH ,  WILLIAM E WILSON

IPC: H05K3/42 ,  H05K1/05 ,  H05K3/00 ,  H05K3/10 ,  H05K3/44

Abstract: PROBLEM TO BE SOLVED: To obtain a circuit card, in which layers made of dielectric material for exposure type latent image formation are used on both opposing surfaces of a metal layer forming a power plane. SOLUTION: This method is provided for forming a printed circuit card. A metal layer 20 which functions as a power plane is sandwiched by a pair of layers 24 and 26 of a photoimageable material, capable of forming a latent with use of a light beam. Photoformed metal-filled vias 46 and photoformed plating through-hole 48 are in a photopatternable material. A signal circuit is formed on the two dielectric layers to be connected to the vias 46 and a through-hole 48. The board has a border 14 in its periphery, and the metal layer 20 has an end which is apart from an end of one 26 of the dielectric layers.

公开(公告)号：MY116051A

公开(公告)日：2003-10-31

申请号：MYPI19994640

申请日：1999-10-27

Applicant: IBM

Inventor： SANJEEV BALWANT SATHE ,  VOYA R MARKOVICH ,  PETER A MOSCHAK ,  SEUNGBAE PARK

IPC: H01L21/50 ,  H01L23/498 ,  H05K1/11 ,  H05K1/02

Abstract: A CHIP CARRIER CONSTITUTED OF AN ORGANIC LAMINATE WHICH INCORPORATES STRUCTURE COMPENSATING FOR THERMAL DEFORMATION OF THE CARRIER. MOREOVER, DISCLOSED IS A METHOD OF COUNTERACTING THE THERMAL DEFORMATIONS ENCOUNTERED BY CHIP CARRIERS, ESPECIALLY DURING SOLDER RETLOW, WHICH IS PREDICATED ON THE UNIFORN1LY, EQUIDISTANT POSITIONING OF METAL-PLATED THROUGH-HOLES (PTH) (10) FORMED IN THE CHIP CARRIER RELATIVE TO CONTACT PADS (12). A PLURALITY OF PLATED THROUGH-HOLES (PTH) ARE POSITIONED EQUIDISTANTLY RELATIVE TO CONTACT (BGA) PADS ON A SURFACE (18) OF A SUBSTRATE (14) WHICH IS CONSTITUTED OF AN ORGANIC LAMINATE MATERIAL, SO AS TO BE ABLE TO CONTROL BOTH IN-PLANE AND OUT-OF-PLANE THERMAL DEFORMATIONS IN THE CHIP CARRIER MATERIAL WHICH MAY BE OCCASIONED IN A SOLDER RETLOW FURNACE OR OVEN. (FIGURE 4A & 4B)