公开(公告)号：JPH1070141A

公开(公告)日：1998-03-10

申请号：JP16599897

申请日：1997-06-23

Applicant: IBM

Inventor： BERNIER WILLIAM EMMETT ,  MICHAEL ANTHONY GEINZU ,  MEMIS IRVING ,  SHAUKATULLAH HUSSAIN

IPC: H01L23/373 ,  H01L21/44 ,  H01L21/52 ,  H01L21/56 ,  H01L21/60 ,  H01L23/34 ,  H01L23/367 ,  H01L23/433 ,  H01L23/42

Abstract: PROBLEM TO BE SOLVED: To provide a method of fitting a radiator or heat sink to an electronic component, and its resultant structure. SOLUTION: A heat sink 118 of aluminum or copper is glued to a ceramic cap 100 or an exposed semiconductor chip by the use of a silicon adhesive or flexible epoxy adhesive 120. Aluminum is covered by anode oxidation or chromate conversion, or copper can be covered by nickel or gold chromium. A structure like this is especially beneficial for fitting a flip chip. These adhesive agents contain materials having high thermal conductivities and low coefficients of thermal expansion(CTE), enhance heat performance, and improve the CTE difference between a silicon metal die and the metal of a heat sink.

公开(公告)号：JP2005142564A

公开(公告)日：2005-06-02

申请号：JP2004319589

申请日：2004-11-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KAWASAKI KAZUSHIGE ,  MEMIS IRVING

IPC: H05K1/18 ,  H01L23/12 ,  H01L23/498 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/46

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/115 ,  H05K3/4602 ,  H05K3/4626 ,  H05K2201/029 ,  H05K2201/09609 ,  H05K2201/09627

Abstract: PROBLEM TO BE SOLVED: To provide a hole pattern for increasing the plated through hole density within a fiber base chip carrier, without the risk of inducing short circuiting by the fiber.
SOLUTION: The plated through hole density within a glass fiber base chip carrier can be enhanced, by placing a hole at a shifted position at which the hole is not connected to a neighboring hole via a fiber. A narrow and long strip zone or region is demarcated, having a width nearly equal to the diameter of the hole and extending in the direction parallel to the direction of the fiber along the row and column of the holes perpendicular to each other defines a region, in which a short circuit may be induced potentially therein. For example, by rotating a conventional X-Y grid pattern, in which holes are arranged at equal intervals so that the hole in one direction is located at every other places between neighboring long and narrow strip zones extending in opposite directions, the interval between holes along the long and narrow strip zone extending in each direction is significantly increased. The hole is located between long and narrow strip zones at a sufficient clearance for compensating the variations in the path of a fiber.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供用于增加光纤基片芯片载体内的电镀通孔密度的孔图案，而不会引起纤维短路的风险。 解决方案：通过在孔未通过光纤连接到相邻孔的偏移位置处设置孔，可以提高玻璃纤维基底芯片载体内的电镀通孔密度。 狭窄且长的带状区域或区域被划分，其宽度几乎等于孔的直径并且沿平行于纤维的方向的方向延伸，沿着彼此垂直的孔的行和列限定了区域， 其中可能潜在地引起短路。 例如，通过旋转传统的XY网格图案，其中孔以相等的间隔布置，使得一个方向上的孔位于沿相反方向延伸的相邻的长条带区域和窄带区域之间的每隔一个位置，沿着 在每个方向上延伸的长而窄的带状区显着增加。 孔以足够的间隙位于长而窄的条带之间，用于补偿光纤路径的变化。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2000294927A

公开(公告)日：2000-10-20

申请号：JP2000092241

申请日：2000-03-29

Applicant: IBM

Inventor： BERND K APPELT ,  JOHN M LAUFER ,  VOYA R MARKOVICH ,  MEMIS IRVING ,  DAVID J RUSSELL

IPC: H05K3/28 ,  H05K3/00 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a method, in which a multilayer circuit board is formed on a board which comprises a first-level circuit pattern on at least one face. SOLUTION: This manufacturing method for a circuit board comprises a process 80, in which a dielectric capable of permanent imaging is formed as to cover a first-level circuit pattern. The manufacturing method contains a process 82, in which the dielectric capable of permanent imaging is exposed to radiation, process 84 in which a conductive metal layer is laminated on the dielectric, a process 86 in which a hole is formed in the conductive metal layer and the dielectric by a laser, a plasma ablation operation or a mechanical drilling operation, a process 8 in which a second-level circuit pattern is formed in which the hole is filled with a conductive material and in which the first-level circuit pattern and the second-level circuit pattern are connected electrically.

公开(公告)号：JP2005159354A

公开(公告)日：2005-06-16

申请号：JP2004335584

申请日：2004-11-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： AUDET JEAN ,  MEMIS IRVING

IPC: H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H05K1/18 ,  H05K3/30

CPC classification number: H05K1/112 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K2201/09227 ,  H05K2201/10674 ,  Y10T29/49155 ,  Y10T29/4916

Abstract: PROBLEM TO BE SOLVED: To provide a multilayer chip carrier with expanded space for power distribution PTHs and reduced power-related noise. SOLUTION: In a multilayer chip carrier with two signal redistribution fanout layers, in addition to signal escape from signal pads near the edges at the first fanout layer, remaining signal pads are moved closer to the edges of the chip footprint. At a voltage layer below the first fanout layer, the remaining signal pads are moved closer to the edges of the chip footprint. In the second fanout layer below the voltage layer, the remaining signal pads are made to escape. Since the signal pads are moved from the central region toward the edges, the space for power PTHs increases. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供具有用于配电PTH的扩展空间的多层芯片载体和降低的功率相关噪声。 解决方案：在具有两个信号再分配扇出层的多层芯片载体中，除了信号从第一扇出层边缘附近的信号焊盘逸出外，剩余的信号焊盘移动到更靠近芯片覆盖区的边缘。 在第一扇出层下方的电压层上，剩余的信号垫移动到更靠近芯片覆盖区的边缘。 在电压层下面的第二扇出层中，剩余的信号垫被排出。 由于信号焊盘从中心区域向边缘移动，所以功率PTH的空间增加。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005150730A

公开(公告)日：2005-06-09

申请号：JP2004328132

申请日：2004-11-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MEMIS IRVING

IPC: H05K1/18 ,  H01L23/12 ,  H01L23/498 ,  H05K1/11 ,  H05K3/46

CPC classification number: H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/112 ,  H05K2201/09227 ,  H05K2201/10674 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a means of improving signal output from a semiconductor chip to a printed wiring board in a flip chip/ball grid array assembly by repositioning signals passing through upper signal layers of a carrier from the chip. SOLUTION: This improvement achieved by signal repositioning involves fanning out, via a chip carrier, circuit lines from the top surface which communicates with a chip through the core to the bottom surface, where signals exit from the carrier to a printed wiring board. This fanning out is achieved by making better use of the surface area of the signal planes between the core and the chip. Signals are fanned out on each of the upper signal planes so that much more signals are transmitted through vias in the core to the bottom signal planes, where the signals can be taken out of the footprint area of the chip, thereby increasing the circuit density taken out of the footprint area. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种通过重新定位穿过来自芯片的载体的上层信号层的信号来改善倒装芯片/球栅阵列组件中的半导体芯片到印刷线路板的信号输出的手段。 解决方案：通过信号重新定位实现的这种改进涉及通过芯片载体从通过芯到芯片的底表面与芯片通信的顶表面扇出电路线，其中信号从载体离开印刷线路板 。 通过更好地利用芯和芯片之间的信号平面的表面积来实现扇形化。 信号在每个上信号平面上扇出，使得更多的信号通过核心中的通孔传输到底部信号平面，其中信号可以从芯片的覆盖区域中取出，从而增加采用的电路密度 离开足迹区域。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JPH10341080A

公开(公告)日：1998-12-22

申请号：JP14549698

申请日：1998-05-27

Applicant: IBM

Inventor： MEMIS IRVING

IPC: H05K3/46 ,  H01L21/60 ,  H01L23/12 ,  H01L23/538 ,  H05K1/11

Abstract: PROBLEM TO BE SOLVED: To provide a multilayered printed circuit board which has a high wiring density. SOLUTION: A circuit board 10 has contacts 20 thereon which are arranged so as to be engaged with contact pads 34 provided on a chip carrier 30 and is defined as a grating. A plurality of primary through-holes 22 are made in the circuit board at corresponding positions in the grating and are electrically connected to the upper chip contact pads. A plurality of secondary through-holes 26 are made in the board as being positioned outside of the grating has an being electrically connected inside of the chip contact pads.

公开(公告)号：HK1019281A1

公开(公告)日：2000-01-28

申请号：HK99103690

申请日：1999-08-27

Applicant: IBM

Inventor： FRANKOSKI EDWARD JAY ,  MEMIS IRVING

IPC: H01L23/498 ,  H05K1/11 ,  H05K3/34 ,  H05K ,  H01L

Abstract: The present invention provides printed circuit boards for mounting to a semiconductor integrated circuit die. In one embodiment the printed circuit boards comprise a rigid dielectric substrate having a planar face, a plurality of circuit lines affixed to the face of the substrate, and a plurality of conductive bumps affixed to the face of the substrate. Each conductive bump has an upper bonding surface that is substantially planar and a lateral surface which is essentially perpendicular to the face of the substrate. The conductive bumps and the circuit lines are formed from a single metallic layer. The conductive bumps and circuit lines constitute a unitary, integral structure, i.e., each conductive bump and connecting circuit line lack a physical interface therebetween. The upper surfaces of the conductive bumps extend to essentially the same height above the surface of the substrate, i.e., the upper surfaces of the conductive bumps are substantially coplanar relative to each other. In another embodiment, the printed circuit board further comprises a unitary solder dam or a plurality of unconnected solder dams that partially or completely surround the conductive bumps. The solder dam has an upper surface which lies below the upper bonding surface of the conductive bump. The solder dam is positioned to prevent the alloy, particularly solder, which is subsequently disposed on each conductive bump from flowing along the circuit lines that are integrally connected to the conductive bump. The present invention also relates to a microelectronic package that comprises a semiconductor integrated circuit die mounted to a printed circuit board made in accordance with the present invention.

公开(公告)号：MY121703A

公开(公告)日：2006-02-28

申请号：MYPI9802013

申请日：1998-05-06

Applicant: IBM

Inventor： MEMIS IRVING

IPC: H05K3/40 ,  H05K3/46 ,  H01L21/60 ,  H01L23/12 ,  H01L23/498 ,  H01L23/538 ,  H05K1/00 ,  H05K1/11

Abstract: A CIRCUIT BOARD (10) IS PROVIDED WHICH HAS CONTACTS (20) ON THE SURFACE (15) ARRAYED TO ENGAGE CONTACT PADS (34) ON A CHIP CARRIER (30) BOUNDED BY A GRID (44). A PLURALITY OF PRIMARY THROUGH HOLES (22) ARE PROVIDED IN THE CIRCUIT BOARD LOCATION WITHIN THE GRID IN AN INTERSTITIAL ARRAY AND ELECTRICALLY CONNECTED TO RESPECTIVE FIRST CHIP CONTACT PADS THEREABOVE. A PLURALITY OF SECONDARY THROUGH HOLES (26) ARE PROVIDED WHICH ARE LOCATED OUTSIDE THE GRID AND ELECTRICALLY CONNECTED TO RESPECTIVE SECOND CHIP CONTACT PADS.

公开(公告)号：FR2335574A1

公开(公告)日：1977-07-15

申请号：FR7632457

申请日：1976-10-18

Applicant: IBM

Inventor： BAKOS PETER ,  MEMIS IRVING ,  RASILE JOHN

IPC: C09D4/00 ,  H01L21/312 ,  H05K5/00 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H05K3/28 ,  H05K5/06 ,  C09D3/82 ,  H01B3/46

Abstract: A hermetic topsealant for metal electrodes on components and other microelectronic circuitry is formed by polymerizing a mixture of an unsaturated silane monomer, a bifunctional silane adhesion promoter, a polymeric plasticizer and a stabilizer.

公开(公告)号：DE69800514T2

公开(公告)日：2001-09-27

申请号：DE69800514

申请日：1998-05-26

Applicant: IBM

Inventor： MEMIS IRVING

IPC: H05K3/46 ,  H01L21/60 ,  H01L23/12 ,  H01L23/538 ,  H05K1/11 ,  H05K3/40 ,  H05K1/00 ,  H01L23/498

Abstract: A circuit board is provided which has contacts on the surface arrayed to engage contact pads on a chip carrier bounded by a grid. A plurality of primary through holes are provided in the circuit board location within the grid in an interstitial array and electrically connected to respective first chip contact pads thereabove. A plurality of secondary through holes are provided which are located outside the grid and electrically connected to respective second chip contact pads.