公开(公告)号：JP2002353174A

公开(公告)日：2002-12-06

申请号：JP2002099896

申请日：2002-04-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GLASHAUSER WALTER ,  UTESS BENNO ,  PURATH ANDREAS

IPC: B24B37/04 ,  B24B49/16 ,  B24B53/007 ,  H01L21/304 ,  B24B37/00 ,  B24B53/02

Abstract: PROBLEM TO BE SOLVED: To provide a method for adjusting the surface of a polishing pad (1) of chemical and mechanical polishing(CMP) of a semiconductor wafer, by measuring the current or voltage of a turntable (2) inputted to a motor (7) for rotating the polishing pad (1) to a rotated adjustment head (4). SOLUTION: The supply power (8) is used as the measure of actual wear for regeneration of the polishing pad (1). Since the polishing pad (1) is degraded generally by repetitive use, that is, contaminats are generated on a surface, wear efficiency is reduced. Therefore, by the method, in the case that a table current deviates from a limit for maintaining uniformity in the adjusting process, an alarm signal (11) is displayed. Especially corresponding to the alarm signal (11), rotation of the polishing pad (1) is accelerated or the pressurizing force or rotation of the adjustment head (4) is increased.

公开(公告)号：DE102004030860A1

公开(公告)日：2005-02-03

申请号：DE102004030860

申请日：2004-06-25

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： BROWN STEPHEN L ,  COSTRINI GREG ,  GAIDIS MICHAEL C ,  FINDEIS FRANK ,  GLASHAUSER WALTER ,  NUETZEL JOACHIM ,  PARK CHANRO ,  O'SULLIVAN EUGENE

IPC: H01L21/4763 ,  H01L21/60 ,  H01L21/768 ,  H01L23/532 ,  H01L27/22

Abstract: Encapsulating areas of metallization in a liner material, such as Tantalum, Tantalum Nitride, Silicon Carbide allows aggressive or harsh processing steps to be used. These aggresive processing steps offer the possibility of fabricating new device architectures. In addition, by encapsulating the areas of metallization, metal ion migration and electromigration can be prevented. Further, the encapsulated areas of metallization can serve as a self-aligning etch mask. Thus, vias etched between adjacent areas of metallization allow the area of the substrate allocated to the via to be significantly reduced without increasing the possibility of electrical shorts to the adjacent areas of metallization.

公开(公告)号：DE102004030860B4

公开(公告)日：2007-05-31

申请号：DE102004030860

申请日：2004-06-25

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： BROWN STEPHEN L ,  COSTRINI GREG ,  GAIDIS MICHAEL C ,  FINDEIS FRANK ,  GLASHAUSER WALTER ,  NUETZEL JOACHIM ,  PARK CHANRO ,  O'SULLIVAN EUGENE

IPC: H01L21/768 ,  H01L21/4763 ,  H01L21/60 ,  H01L23/532 ,  H01L27/22

Abstract: Encapsulating areas of metallization in a liner material, such as Tantalum, Tantalum Nitride, Silicon Carbide allows aggressive or harsh processing steps to be used. These aggresive processing steps offer the possibility of fabricating new device architectures. In addition, by encapsulating the areas of metallization, metal ion migration and electromigration can be prevented. Further, the encapsulated areas of metallization can serve as a self-aligning etch mask. Thus, vias etched between adjacent areas of metallization allow the area of the substrate allocated to the via to be significantly reduced without increasing the possibility of electrical shorts to the adjacent areas of metallization.

公开(公告)号：DE102004029355A1

公开(公告)日：2005-02-17

申请号：DE102004029355

申请日：2004-06-17

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： COSTRINI GREG ,  GAIDIS MICHAEL C ,  RATH DAVID L ,  GLASHAUSER WALTER

IPC: H01L21/60 ,  H01L21/283 ,  H01L21/311 ,  H01L21/3213

公开(公告)号：DE60121292T2

公开(公告)日：2007-07-05

申请号：DE60121292

申请日：2001-04-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GLASHAUSER WALTER ,  UTESS BENNO ,  PURATH ANDREAS DR

IPC: B24B49/16 ,  B24B37/04 ,  B24B53/00 ,  B24B53/007 ,  H01L21/304

公开(公告)号：DE60113972T2

公开(公告)日：2006-05-11

申请号：DE60113972

申请日：2001-03-14

Applicant: FREESCALE SEMICONDUCTOR INC ,  SEMICONDUCTOR 300 GMBH & CO KG ,  INFINEON TECHNOLOGIES AG

Inventor： GLASHAUSER WALTER ,  TEICHGRAEBER LUTZ ,  HAGGART DAVID ,  EBNER KATRIN

IPC: B24B37/30 ,  B24B49/16 ,  H01L21/304 ,  H01L21/683

Abstract: A polishing head (200) for a chemical-mechanical polishing machine that holds a semiconductor wafer (150) against a polishing pad (140) has a chuck (295) with a pressure chamber (210) to apply a down force substantially equally to the wafer backside (152). An electrode arrangement (270) within the chamber (210) is located coplanar to the wafer (150) to provide compensation to wafer or chuck irregularities by applying a compensation force having a distribution corresponding to the irregularities.

公开(公告)号：DE60113972D1

公开(公告)日：2006-02-23

申请号：DE60113972

申请日：2001-03-14

Applicant: FREESCALE SEMICONDUCTOR INC ,  SEMICONDUCTOR 300 GMBH & CO KG ,  INFINEON TECHNOLOGIES AG

Inventor： GLASHAUSER WALTER ,  TEICHGRAEBER LUTZ ,  HAGGART DAVID ,  EBNER KATRIN

IPC: B24B37/30 ,  B24B49/16 ,  H01L21/304 ,  H01L21/683

Abstract: A polishing head (200) for a chemical-mechanical polishing machine that holds a semiconductor wafer (150) against a polishing pad (140) has a chuck (295) with a pressure chamber (210) to apply a down force substantially equally to the wafer backside (152). An electrode arrangement (270) within the chamber (210) is located coplanar to the wafer (150) to provide compensation to wafer or chuck irregularities by applying a compensation force having a distribution corresponding to the irregularities.

公开(公告)号：DE60121292D1

公开(公告)日：2006-08-17

申请号：DE60121292

申请日：2001-04-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GLASHAUSER WALTER ,  UTESS BENNO ,  PURATH ANDREAS DR

IPC: B24B49/16 ,  B24B37/04 ,  B24B53/00 ,  B24B53/007 ,  H01L21/304

公开(公告)号：JPH1126595A

公开(公告)日：1999-01-29

申请号：JP11649898

申请日：1998-04-27

Applicant: IBM ,  SIEMENS AG

Inventor： LEVY MAX GERALD ,  FIEGL BERNHARD ,  GLASHAUSER WALTER ,  PREIN FRANK

IPC: H01L21/76 ,  H01L21/304 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To make shallow trench separation by a method wherein a conformal silicon oxide layer on a mesa is partially etched by selective RIE and then the silicon oxide layer is transformed to a flat silicon oxide layer using a silicon nitride pad as an etch stopper and then a conformal blanket silicon oxide layer is polished chemically and mechanically. SOLUTION: An RIE etchant is introduced from openings 48A, 48B, 48C into etching openings 50A, 50B, 50C formed inside through a gate insulating layer 44 extended through a tungsten silicide layer 42 and a doped polysilicon layer 40. Then, the surfaces of gate oxide layer segments 38/38' are exposed with a gate conductor stack 51 having source/drain windows on both sides of an N well 34 and having a dummy window wherein a P well is exposed for the later ion implantation being left over. After that, the entire surface is covered by the silicon nitride gate insulating layer 44 and then the insulating layer 44 is polished chemically and mechanically.

公开(公告)号：JPH10294362A

公开(公告)日：1998-11-04

申请号：JP9896898

申请日：1998-04-10

Applicant: IBM ,  SIEMENS AG

Inventor： FIEGL BERNHARD ,  GLASHAUSER WALTER ,  LEVY MAX G ,  NASTASI VICTOR R

IPC: H01L21/76 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/762

Abstract: PROBLEM TO BE SOLVED: To enable a process through which a shallow trench is filled in to be enhanced in manufacturing properties and yield by a method wherein an intermediate plane layer is formed, and the lower layer of a thick oxide is selectively etched to deteriorate in planarity. SOLUTION: An upper planar surface is formed so as to be flush with the fill-in upper surface 115 of a fill-in layer 110. A polish stop layer 130 is removed by the use of etching chemicals which are capable of etching both the polish stop layer 130 and a temporary fill-in layer 120, and an intermediate plane surface is kept unremoved leaving the cover part of the temporary fill-in layer 120 unremoved. A part of the fill-in layer 110 located outside the cover part of the temporary fill-in layer 120 is etched as deep as a point shallower than a trench by the use of chemicals which etch the fill-in layer 110 preferentially so as to enable the fill-in upper surface 115 of the fill-in layer 110 located above a reference surface to be flush with the fill-in upper surface 115 of the fill-in layer 110 located in the trench, whereby a planar surface is deteriorated in flatness.