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    METHOD FOR ADJUSTING POLISHING PAD SURFACE, AND DEVICE THEREOF
    1.
    发明专利
    METHOD FOR ADJUSTING POLISHING PAD SURFACE, AND DEVICE THEREOF 审中-公开

    公开(公告)号：JP2002353174A

    公开(公告)日：2002-12-06

    申请号：JP2002099896

    申请日：2002-04-02

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GLASHAUSER WALTER ,  UTESS BENNO ,  PURATH ANDREAS

    IPC: B24B37/04 ,  B24B49/16 ,  B24B53/007 ,  H01L21/304 ,  B24B37/00 ,  B24B53/02

    Abstract: PROBLEM TO BE SOLVED: To provide a method for adjusting the surface of a polishing pad (1) of chemical and mechanical polishing(CMP) of a semiconductor wafer, by measuring the current or voltage of a turntable (2) inputted to a motor (7) for rotating the polishing pad (1) to a rotated adjustment head (4). SOLUTION: The supply power (8) is used as the measure of actual wear for regeneration of the polishing pad (1). Since the polishing pad (1) is degraded generally by repetitive use, that is, contaminats are generated on a surface, wear efficiency is reduced. Therefore, by the method, in the case that a table current deviates from a limit for maintaining uniformity in the adjusting process, an alarm signal (11) is displayed. Especially corresponding to the alarm signal (11), rotation of the polishing pad (1) is accelerated or the pressurizing force or rotation of the adjustment head (4) is increased.

    5.
    发明专利
    未知

    公开(公告)号：DE102004030860A1

    公开(公告)日：2005-02-03

    申请号：DE102004030860

    申请日：2004-06-25

    Applicant: IBM ,  INFINEON TECHNOLOGIES AG

    Inventor： BROWN STEPHEN L ,  COSTRINI GREG ,  GAIDIS MICHAEL C ,  FINDEIS FRANK ,  GLASHAUSER WALTER ,  NUETZEL JOACHIM ,  PARK CHANRO ,  O'SULLIVAN EUGENE

    IPC: H01L21/4763 ,  H01L21/60 ,  H01L21/768 ,  H01L23/532 ,  H01L27/22

    Abstract: Encapsulating areas of metallization in a liner material, such as Tantalum, Tantalum Nitride, Silicon Carbide allows aggressive or harsh processing steps to be used. These aggresive processing steps offer the possibility of fabricating new device architectures. In addition, by encapsulating the areas of metallization, metal ion migration and electromigration can be prevented. Further, the encapsulated areas of metallization can serve as a self-aligning etch mask. Thus, vias etched between adjacent areas of metallization allow the area of the substrate allocated to the via to be significantly reduced without increasing the possibility of electrical shorts to the adjacent areas of metallization.

    6.
    发明专利
    未知

    公开(公告)号：DE102004030860B4

    公开(公告)日：2007-05-31

    申请号：DE102004030860

    申请日：2004-06-25

    Applicant: IBM ,  INFINEON TECHNOLOGIES AG

    Inventor： BROWN STEPHEN L ,  COSTRINI GREG ,  GAIDIS MICHAEL C ,  FINDEIS FRANK ,  GLASHAUSER WALTER ,  NUETZEL JOACHIM ,  PARK CHANRO ,  O'SULLIVAN EUGENE

    IPC: H01L21/768 ,  H01L21/4763 ,  H01L21/60 ,  H01L23/532 ,  H01L27/22

    Abstract: Encapsulating areas of metallization in a liner material, such as Tantalum, Tantalum Nitride, Silicon Carbide allows aggressive or harsh processing steps to be used. These aggresive processing steps offer the possibility of fabricating new device architectures. In addition, by encapsulating the areas of metallization, metal ion migration and electromigration can be prevented. Further, the encapsulated areas of metallization can serve as a self-aligning etch mask. Thus, vias etched between adjacent areas of metallization allow the area of the substrate allocated to the via to be significantly reduced without increasing the possibility of electrical shorts to the adjacent areas of metallization.

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