公开(公告)号：DE102004030860B4

公开(公告)日：2007-05-31

申请号：DE102004030860

申请日：2004-06-25

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： BROWN STEPHEN L ,  COSTRINI GREG ,  GAIDIS MICHAEL C ,  FINDEIS FRANK ,  GLASHAUSER WALTER ,  NUETZEL JOACHIM ,  PARK CHANRO ,  O'SULLIVAN EUGENE

IPC: H01L21/768 ,  H01L21/4763 ,  H01L21/60 ,  H01L23/532 ,  H01L27/22

Abstract: Encapsulating areas of metallization in a liner material, such as Tantalum, Tantalum Nitride, Silicon Carbide allows aggressive or harsh processing steps to be used. These aggresive processing steps offer the possibility of fabricating new device architectures. In addition, by encapsulating the areas of metallization, metal ion migration and electromigration can be prevented. Further, the encapsulated areas of metallization can serve as a self-aligning etch mask. Thus, vias etched between adjacent areas of metallization allow the area of the substrate allocated to the via to be significantly reduced without increasing the possibility of electrical shorts to the adjacent areas of metallization.

公开(公告)号：DE102004029355A1

公开(公告)日：2005-02-17

申请号：DE102004029355

申请日：2004-06-17

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： COSTRINI GREG ,  GAIDIS MICHAEL C ,  RATH DAVID L ,  GLASHAUSER WALTER

IPC: H01L21/60 ,  H01L21/283 ,  H01L21/311 ,  H01L21/3213

公开(公告)号：DE102005036073A1

公开(公告)日：2006-03-23

申请号：DE102005036073

申请日：2005-08-01

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GAIDIS MICHAEL C ,  LEUSCHNER RAINER ,  ROMANKIW LUBOMYR TARAS ,  RUBINO JUDY M

IPC: H01L27/22 ,  H01L21/768

Abstract: A method of forming a ferromagnetic liner on conductive lines of magnetic memory devices and a structure thereof. The ferromagnetic liner increases the flux concentration of current run through the conductive lines, reducing the amount of write current needed to switch magnetic memory cells. The conductive lines are formed in a plate-up method, and the ferromagnetic liner is selectively formed on the plated conductive lines. The ferromagnetic liner may also be formed over conductive lines and a top portion of vias in a peripheral region of the workpiece.

公开(公告)号：DE102004030860A1

公开(公告)日：2005-02-03

申请号：DE102004030860

申请日：2004-06-25

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： BROWN STEPHEN L ,  COSTRINI GREG ,  GAIDIS MICHAEL C ,  FINDEIS FRANK ,  GLASHAUSER WALTER ,  NUETZEL JOACHIM ,  PARK CHANRO ,  O'SULLIVAN EUGENE

IPC: H01L21/4763 ,  H01L21/60 ,  H01L21/768 ,  H01L23/532 ,  H01L27/22

Abstract: Encapsulating areas of metallization in a liner material, such as Tantalum, Tantalum Nitride, Silicon Carbide allows aggressive or harsh processing steps to be used. These aggresive processing steps offer the possibility of fabricating new device architectures. In addition, by encapsulating the areas of metallization, metal ion migration and electromigration can be prevented. Further, the encapsulated areas of metallization can serve as a self-aligning etch mask. Thus, vias etched between adjacent areas of metallization allow the area of the substrate allocated to the via to be significantly reduced without increasing the possibility of electrical shorts to the adjacent areas of metallization.

公开(公告)号：EP1911096A4

公开(公告)日：2008-10-22

申请号：EP06788341

申请日：2006-07-24

Applicant: IBM

Inventor： DALTON TIMOTHY J ,  HSU LOUIS L C ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO ,  GAIDIS MICHAEL C ,  RADENS CARL ,  CLEVENGER LAWRENCE A

IPC: H01L27/22 ,  H01L21/768 ,  H01L21/8247 ,  H01L23/528 ,  H01L43/12

CPC classification number: B82Y10/00 ,  H01L27/222 ,  H01L43/12

Abstract: A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.

公开(公告)号：EP1642330A4

公开(公告)日：2011-09-28

申请号：EP03817676

申请日：2003-06-24

Applicant: IBM

Inventor： GAIDIS MICHAEL C

IPC: H01L21/46 ,  H01L21/301 ,  H01L21/321 ,  H01L21/762 ,  H01L21/78 ,  H01L21/8246 ,  H01L23/544 ,  H01L27/22

CPC classification number: H01L21/3212 ,  B82Y10/00 ,  H01L23/544 ,  H01L27/222 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1917678A4

公开(公告)日：2012-08-22

申请号：EP06759161

申请日：2006-05-04

Applicant: IBM

Inventor： KANAKASABAPATHY SIVANANDA K ,  GAIDIS MICHAEL C

IPC: H01L21/00 ,  H01L21/26 ,  H01L21/302 ,  H01L29/78

CPC classification number: H01L43/12 ,  H01L21/76897 ,  H01L27/222 ,  H01L43/08 ,  H01L2924/3011

公开(公告)号：EP2140458A4

公开(公告)日：2010-05-05

申请号：EP07867608

申请日：2007-12-04

Applicant: IBM

Inventor： GAIDIS MICHAEL C ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  DEBROSSE JOHN K ,  HSU LOUIS L C ,  RADENS CARL ,  WONG KEITH K H ,  YANG CHIH-CHAO

IPC: G11C19/08 ,  G11B5/008

CPC classification number: G11C19/0841 ,  B82Y10/00 ,  G11C5/02 ,  G11C11/161 ,  G11C11/1675 ,  Y10T29/53165

公开(公告)号：EP1908094A4

公开(公告)日：2009-02-11

申请号：EP05853232

申请日：2005-12-07

Applicant: IBM

Inventor： GAIDIS MICHAEL C ,  KANAKASABAPATHY SIVANANDA K ,  O'SULLIVAN EUGENE J

IPC: H01L21/00 ,  B05C1/00 ,  B44C1/22

CPC classification number: H01L43/12 ,  H01L21/0332 ,  H01L21/0337 ,  H01L27/11507 ,  H01L28/65

Abstract: Techniques for magnetic device (302) fabrication are provided. In one aspect, a method of patterning at least one, e.g., nonvolatile, material comprises the following steps. A hard mask structure (315), comprising thin hard mask layer (316) and thick hard mask layer (318) is formed on at least one surface of the material to be patterned. The hard mask structure is configured to have a base, proximate to the material, and a top opposite the base. The base has one~ or more lateral dimensions that are greater than one or more lateral dimensions of the top of the hard mask structure, such that at least one portion of the base extends out laterally a substantial distance beyond the top. The top of the hard mask structure is at a greater vertical distance from the material being etched than the base. The material is etched.

公开(公告)号：EP1639653A4

公开(公告)日：2006-11-22

申请号：EP03817675

申请日：2003-06-24

Applicant: IBM

Inventor： GAIDIS MICHAEL C

IPC: H01L29/82 ,  G11C11/15 ,  G11C11/16 ,  H01L27/22 ,  H01L29/00 ,  H01L43/00 ,  H01L43/08 ,  H01L43/12

CPC classification number: G11C11/16 ,  H01L27/222 ,  H01L43/08 ,  H01L43/12

Abstract: A conductive line structure for a field effect transistor (FET) based magnetic random access memory (MRAM) device includes a lateral metal strap (326) conductively coupled to a lower metallization line (302). A magnetic tunnel junction (MTJ) stack (316) is formed on the metal strap (326), and a metal shield (324) is formed over the MTJ stack (316), the metal shield (324) being self-aligned with respect to the metal strap (326). An upper metallization line (332) is conductively coupled to the metal shield (324), wherein the metal shield (324) serves as an etch stop during the formation of the upper metallization line (332).