公开(公告)号：JP2000339990A

公开(公告)日：2000-12-08

申请号：JP2000115370

申请日：2000-04-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  PFEFFERL KARL-PETER

IPC: G06F12/16 ,  G06F11/20 ,  G11C11/401 ,  G11C11/409 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To allow a plurality of redundant data lines to be flexibly associated with different groups by allowing a bus line on a first plane to be connected to all of input/output lines and all of data lines and allowing a plurality of independent partial buses on a second plane to be connected to data lines in at least two groups and an input/output line of each one group. SOLUTION: Data lines MDQii, of groups U1 to U8 are respectively connectable to IO lines RWDii of groups IO1 to IO4 via bus systems on two planes. All of bus lines Ai on a first plane A are connectable to all of data lines MDQ11, to MDQ88, redundant lines MDQ1R to MDQ8R, and IO lines RWD11 to RWD48. Bus lines Bi1 to Bi8 on a second plane composed of partial buses B1 to B4 are respectively connectable to two groups of the data lines MDQi1 to MDQi8, the redundant line MDQR, and one group of the IO lines RWDi1 to RWDi8.

公开(公告)号：JP2002198442A

公开(公告)日：2002-07-12

申请号：JP2001340062

申请日：2001-11-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  KAISER ROBERT ,  PFEFFERL KARL-PETER ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT

IPC: G11C11/401 ,  G11C5/02 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/50 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a memory block having a flexible structure. SOLUTION: The memory structure has a contact block (1), and cell blocks (2-9) adjacent to the contact block (1). The contact block (1) is located in the center, the cell blocks (2-9) abut on the four sides of the contact block (1), respectively, and the cell blocks (2-9) are arranged annularly around the contact block (1). The cell block (2) has two sides abutting, respectively, on two other cell blocks (3, 9) and the cell blocks (2-9) are divided into first and second sub-cell blocks (21, 22) in the longitudinal direction.

公开(公告)号：JP2001118386A

公开(公告)日：2001-04-27

申请号：JP2000280771

申请日：2000-09-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  PFEFFERL KARL-PETER

IPC: G11C11/407 ,  G11C8/08 ,  G11C8/12 ,  G11C8/14 ,  G11C11/401

Abstract: PROBLEM TO BE SOLVED: To hold less horizontal lines by allowing 512 bits per a bit line or more in a structure body of a word line segmented. SOLUTION: This device is provided with two word lines (MWL0 and MWL1), sub-word lines(SWL) are arranged at those lines alternately, Thereby, two memory banks can be allotted to the sub-word lines alternately.

公开(公告)号：DE102004041896B4

公开(公告)日：2006-05-18

申请号：DE102004041896

申请日：2004-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  MINZONI ALESSANDRO

IPC: H03K5/153

Abstract: The device (101) has a delay mechanism with a variably controllable delay time (tvar) and into which a clock signal (CLK) is input and then issued as a delayed clock signal (DCLK). A phase comparator (104) compares the phase of the signal (CLK) with the phase of the signal (DCLK). A control device (116) for activating and/or deactivating the device (101) based on a control signal that is evaluated by an evaluating device. - An INDEPENDENT CLAIM is also included for method for synchronizing a clock signal.

公开(公告)号：DE102004041896A1

公开(公告)日：2006-03-09

申请号：DE102004041896

申请日：2004-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  MINZONI ALESSANDRO

IPC: H03K5/153

Abstract: The device (101) has a delay mechanism with a variably controllable delay time (tvar) and into which a clock signal (CLK) is input and then issued as a delayed clock signal (DCLK). A phase comparator (104) compares the phase of the signal (CLK) with the phase of the signal (DCLK). A control device (116) for activating and/or deactivating the device (101) based on a control signal that is evaluated by an evaluating device. An independent claim is also included for method for synchronizing a clock signal.

公开(公告)号：DE102004004775A1

公开(公告)日：2005-08-25

申请号：DE102004004775

申请日：2004-01-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN

IPC: G05F1/10 ,  G05F1/46 ,  G11C5/14

公开(公告)号：DE10339665B3

公开(公告)日：2005-01-13

申请号：DE10339665

申请日：2003-08-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN

IPC: G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/401 ,  G11C5/02

Abstract: The method involves activating memory cells of a first sub-array, accessing the corresponding cells, and leaving the sub-array cells in the active state if an access is to be made to one or more further memory cells contained in a second sub-array of the same memory cell array. The cells of the first sub-array are deactivated only if access to additional cells is to be made that are contained in a third memory cell sub-array, if the sense amplifiers of this sub-array are also used by the first sub-array. An independent claim is included for a semiconductor memory device.

公开(公告)号：DE10230168B9

公开(公告)日：2004-09-16

申请号：DE10230168

申请日：2002-07-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  MINZONI ALESSANDRO

IPC: G05F5/08 ,  G11C7/10 ,  H03G3/00 ,  H03K3/356 ,  H03K5/01 ,  H03L5/00

Abstract: The invention involves a voltage converter device ( 101 a , 101 b) for converting a signal (in) at an initial voltage level (vint) into a signal (DatoV) at a second voltage level (vint) differing from the first, in which voltage converter device ( 101 a , 101 b) has an amplifier device ( 102 ), and where the amplifier device ( 102 ) uses a second amplifier device output signal (bout) to generate signals (DatoV) at the second voltage level (vddq).

公开(公告)号：DE10261409A1

公开(公告)日：2004-07-22

申请号：DE10261409

申请日：2002-12-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  MINZONI ALESSANDRO

IPC: H03K5/00 ,  H03L7/081 ,  H03K5/15

Abstract: The delay locked loop includes an additional delay element (102) connected in series with a first delay element (101). A frequency detector unit (110) detects the frequency of the input signal (103). The second delay element is adjustable based on the detected frequency of the input signal. Independent claims are included for a frequency detector unit and a method of providing clock signals in circuit units.

公开(公告)号：DE10211912A1

公开(公告)日：2003-10-16

申请号：DE10211912

申请日：2002-03-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN

IPC: H02J1/10 ,  G05F1/62 ,  H01L23/58

Abstract: The device is externally supplied with a supply voltage and has at least one useful circuit and a current supply for the useful circuit(s) with several current supply units. The current supply has a control unit (18) for comparing the supply voltage with a predefined demand value and for switching one or more switchable current supply units on or off depending on the comparison result. AN Independent claim is also included for the following: a method of controling a current supply for an integrated circuit.