中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

75 records (took 0.026 seconds)

    INTEGRATED DRAM MEMORY CELL AND DRAM MEMORY
    1.
    发明专利
    INTEGRATED DRAM MEMORY CELL AND DRAM MEMORY 失效

    公开(公告)号：JP2001291848A

    公开(公告)日：2001-10-19

    申请号：JP2001068253

    申请日：2001-03-12

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FREY ALEXANDER ,  WEBER WERNER ,  SCHLOSSER TILL

    IPC: H01L27/108 ,  G11C11/407 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/02

    Abstract: PROBLEM TO BE SOLVED: To decrease an area of a DRAM memory cell. SOLUTION: A memory cell 51 has at least a memory capacitor 52 and a selection transistor 12 which are intrinsically formed in a region of a rectangular cell region 59. The rectangular cell region 59 has a larger range in a longitudinal direction L than in a widthwise direction B. It is wired to a periphery of a cell via word lines 56, 57 and a bit line 55, or can be wired thereto. The word lines 56, 57 and the bit line 55 are transmitted onto the memory cell 51 and are directed at least intrinsically perpendicular to each other.

    MAGNETORESISTIVE MEMORY AND READING METHOD THEREOF
    2.
    发明专利
    MAGNETORESISTIVE MEMORY AND READING METHOD THEREOF 审中-公开

    公开(公告)号：JP2002133856A

    公开(公告)日：2002-05-10

    申请号：JP2001266554

    申请日：2001-09-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： THEWES ROLAND ,  WEBER WERNER ,  BERG HUGO VAN DEN

    IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16

    Abstract: PROBLEM TO BE SOLVED: To provide a suitable architecture for reliable write, read and erase of magnetoresistive memory cells in a memory cell structure (namely, magnetoresistive memory). SOLUTION: The magnetoresistive memory is provided with a structure of magnetoresistive memory cells arranged in plural rows and/or plural columns, bit lines for each of the columns connected to a 1st electrode of the memory cells belonging to the columns, word lines for each of the rows connected to a 2nd electrode of the memory cells belonging to the rows, a reading voltage source which can individually be connected to the 1st end part of the word lines via switching elements, and a voltage evaluation means at least one of the inputs of which can individually be connected by the switching elements to the 1st end part of the bit lines via an evaluation line.

    WRITE/READ CIRCUIT FOR DRAM MEMORY
    3.
    发明专利
    WRITE/READ CIRCUIT FOR DRAM MEMORY 失效

    公开(公告)号：JP2001298166A

    公开(公告)日：2001-10-26

    申请号：JP2001053052

    申请日：2001-02-27

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FREY ALEXANDER ,  WEBER WERNER ,  SCHLOESSER TILL

    IPC: G11C11/4091 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To provide a read/write circuit which can be inserted into even the reduced raster of 4F width in DRAM memory components since a DRAM uses the write/read circuit for refreshing information and requires an integrated write/read circuit for evaluating at least one bit line, and high integration is required for the write/read circuit on the other hand as well. SOLUTION: At least one transistor to be used for the write/read circuit is a longitudinal type transistor. Besides, source/drain areas 57 and 59 of each of paired transistor are made common.

    MAGNETORESISTIVE MEMORY AND METHOD FOR READING OUT FROM THE SAME
    4.
    发明申请
    MAGNETORESISTIVE MEMORY AND METHOD FOR READING OUT FROM THE SAME 审中-公开
    磁阻存储器和读出方法FOR HIS

    公开(公告)号：WO0247089A2

    公开(公告)日：2002-06-13

    申请号：PCT/DE0104400

    申请日：2001-11-22

    Applicant: INFINEON TECHNOLOGIES AG ,  THEWES ROLAND ,  WEBER WERNER ,  BERG HUGO VAN DEN

    Inventor： THEWES ROLAND ,  WEBER WERNER ,  VAN DEN BERG HUGO

    IPC: G11C11/15 ,  G11C11/16 ,  H01L43/08 ,  G11C11/00

    CPC classification number: G11C11/15 ,  G11C11/16

    Abstract: The invention relates to a magnetoresistive memory and is characterized by a control circuit (1) with a first pole which, via a reading distributor (14), can be individually connected to first ends of bit lines (4a, 4b) by means of switching elements (8a, 8b). Said control circuit also has a second pole, which supplies power to an evaluator (2), and has a third pole that is connected to a reference voltage source (U5). The readout circuit additionally comprises a third voltage source (U3) having a voltage, which is approximately equal to the voltage of the first reading voltage source (U1) and which can be individually connected to second ends of the bit lines (4a, 4b) by means of switching elements (9a, 9b). Finally, the readout circuit comprises a fourth voltage source (U4), which can be individually connected to second ends of the word lines (5a, 5b) by means of switching elements (7a, 7b).

    Abstract translation: 用于磁 - 电阻性存储器的读出电路，其包括具有第一端的控制电路（1）的经由读分配器（14）由开关元件（8A，8B）与位线的第一端（4A，4B）可被单独地连接; 在评估器（一个或多个）将其当前的第二极; 连接，以及第三极，其连接到基准电压源（U5）; 第三电压源（U3）具有电压近似等于所述第一读取电压源（U1）的电压和通过开关元件89A，9B）与位线（4a的第二端部，4B）可被单独地连接; 和第四电压源（U4），它经由开关元件（7A，7B）的字线的第二端（5A，5B）可以被单独地连接。

    Verfahren zum Herstellen eines graphenbasierten Sensors
    8.
    发明专利
    Verfahren zum Herstellen eines graphenbasierten Sensors 未知

    公开(公告)号：DE102018214302B4

    公开(公告)日：2020-07-30

    申请号：DE102018214302

    申请日：2018-08-23

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GLACER CHRISTOPH ,  PINDL STEPHAN ,  WITTMANN SEBASTIAN ,  WEBER WERNER

    IPC: B81C1/00 ,  B81B7/02 ,  G01L7/00 ,  H01L43/14 ,  H04R19/04

    Abstract: Verfahren zum Herstellen eines graphenbasierten Sensors (1), wobei das Verfahren folgende Schritte umfasst:Bereitstellen eines Trägersubstrates (2);Ausbilden einer Trägerstruktur (3) an dem Trägersubstrat (2), derart, dass an einer Oberseite (4) der Trägerstruktur (3) eine oder mehrere Trennstrukturen (5) ausgebildet werden; undnasschemischer Transfer einer Graphenschicht (6) auf die Oberseite (4) der Trägerstruktur (3), welche die Trennstrukturen (5) aufweist;wobei die Trennstrukturen (5) und eine Reißfestigkeit der Graphenschicht (6) so aufeinander abgestimmt sind, dass die Graphenschicht (6) bei dem nasschemischen Transfer jeweils an den Trennstrukturen (5) einreißt;wobei die Trägerstruktur (3) so ausgebildet wird, dass sie eine Öffnung (12) aufweist, und wobei der nasschemische Transfer so durchgeführt wird, dass ein erster Abschnitt (13) der Graphenschicht (6) die Öffnung (12) abdeckt, und dass ein zweiter Abschnitt (14) der Graphenschicht (6) einen die Öffnung (12) umgebenden Bereich der Trägerstruktur (3) abdeckt;wobei der Sensor (1) als Hall-Sensor (1), als Mikrophon (1) oder als Drucksensor ausgebildet wird, wobei der erste Abschnitt der Graphenschicht (13) zum Wandeln einer zu detektierenden physikalischen Größe in ein elektrisches Signal ausgebildet wird.

Patent Agency Ranking