公开(公告)号：US11528811B2

公开(公告)日：2022-12-13

申请号：US17336008

申请日：2021-06-01

Applicant: INTEL CORPORATION

Inventor： Jeremy Ecton ,  Nicholas Haehn ,  Oscar Ojeda ,  Arnab Roy ,  Timothy White ,  Suddhasattwa Nad ,  Hsin-Wei Wang

IPC: H05K3/46 ,  H01L21/48 ,  H01L23/498 ,  H05K3/18 ,  H05K5/00

Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.

公开(公告)号：US11373951B2

公开(公告)日：2022-06-28

申请号：US15937645

申请日：2018-03-27

Applicant: INTEL CORPORATION

Inventor： Jeremy D. Ecton ,  Hiroki Tanaka ,  Oscar Ojeda ,  Arnab Roy ,  Vahidreza Parichehreh ,  Leonel R. Arana ,  Chung Kwang Tan ,  Robert A. May

IPC: H01L23/538 ,  H01L21/48

Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

公开(公告)号：US20200236795A1

公开(公告)日：2020-07-23

申请号：US16634804

申请日：2017-09-27

Applicant: INTEL CORPORATION

Inventor： Jeremy Ecton ,  Nicholas Haehn ,  Oscar Ojeda ,  Arnab Roy ,  Timothy White ,  Suddhasattwa Nad ,  Hsin-Wei Wang

IPC: H05K3/46 ,  H05K5/00 ,  H05K3/18 ,  H01L23/498 ,  H01L21/48

Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.

公开(公告)号：US11116084B2

公开(公告)日：2021-09-07

申请号：US16634804

申请日：2017-09-27

Applicant: INTEL CORPORATION

Inventor： Jeremy Ecton ,  Nicholas Haehn ,  Oscar Ojeda ,  Arnab Roy ,  Timothy White ,  Suddhasattwa Nad ,  Hsin-Wei Wang

IPC: H05K3/46 ,  H01L21/48 ,  H01L23/498 ,  H05K3/18 ,  H05K5/00

Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.

公开(公告)号：US10515824B2

公开(公告)日：2019-12-24

申请号：US15868942

申请日：2018-01-11

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Leonel Arana ,  Nicholas S. Haehn ,  Hsin-Wei Wang ,  Oscar Ojeda ,  Arnab Roy

IPC: H01L21/321 ,  H01L21/3213 ,  C23F1/14 ,  H01L21/48

Abstract: A method of anisotropic etching comprises forming a metal layer above a substrate. A mask layer is formed on the metal layer with openings defined in the mask layer to expose portions of the metal layer. The exposed portions of the metal layer are introduced to an active etchant solution that includes nanoparticles as an insoluble banking agent. In further embodiments, the exposed portions of the metal layer are introduced to a magnetic and/or an electrical field.

公开(公告)号：US20190304912A1

公开(公告)日：2019-10-03

申请号：US15937645

申请日：2018-03-27

Applicant: INTEL CORPORATION

Inventor： Jeremy D. Ecton ,  Hiroki Tanaka ,  Oscar Ojeda ,  Arnab Roy ,  Vahidreza Parichehreh ,  Leonel R. Arana ,  Chung Kwang Tan ,  Robert A. May

IPC: H01L23/538 ,  H01L21/48

Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

公开(公告)号：US20190304890A1

公开(公告)日：2019-10-03

申请号：US15942864

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Hiroki Tanaka ,  Kristof Kuwawi Darmawikarta ,  Oscar Ojeda ,  Arnab Roy ,  Nicholas Haehn

IPC: H01L23/498 ,  H01L23/14 ,  H01L23/00 ,  H01L21/48 ,  H01L21/027 ,  G03F7/039 ,  G03F7/038 ,  G03F7/20 ,  G03F7/26

Abstract: Disclosed herein are via-trace structures with improved alignment, and related package substrates, packages, and computing device. For example, in some embodiments, a package substrate may include a conductive trace, and a conductive via in contact with the conductive trace. The alignment offset between the conductive trace and the conductive via may be less than 10 microns, and conductive trace may have a bell-shaped cross-section or the conductive via may have a flared shape.

公开(公告)号：US20180286700A1

公开(公告)日：2018-10-04

申请号：US15474302

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： Jeremy D. Ecton ,  Changhua Liu ,  Arnab Roy ,  Oscar U. Ojeda ,  Timothy A. White ,  Nicholas S. Haehn

IPC: H01L21/3213 ,  H01L21/67

CPC classification number: H01L21/32134 ,  H01L21/32139 ,  H01L21/6708 ,  H05K3/067

Abstract: The systems and methods described herein use at least one etchant and at least one photochemically active material in conjunction with electromagnetic energy applied simultaneous with the etchant and photochemically active material during the etching process. The interaction between the electromagnetic energy and the photochemically active material preferentially increases the etch rate in a direction along the axis of incidence of the electromagnetic energy, thereby permitting the anisotropic formation of voids within the semiconductor substrate. These anisotropic voids may be more closely spaced (i.e., arranged on a tighter pitch) than the isotropic voids produced using conventional etching technologies. By placing the voids in the semiconductor substrate on a tighter pitch, greater component density may be achieved.

公开(公告)号：US10438812B2

公开(公告)日：2019-10-08

申请号：US15474302

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： Jeremy D. Ecton ,  Changhua Liu ,  Arnab Roy ,  Oscar U. Ojeda ,  Timothy A. White ,  Nicholas S. Haehn

IPC: H01L21/3213 ,  H05K3/06 ,  H01L21/67

Abstract: The systems and methods described herein use at least one etchant and at least one photochemically active material in conjunction with electromagnetic energy applied simultaneous with the etchant and photochemically active material during the etching process. The interaction between the electromagnetic energy and the photochemically active material preferentially increases the etch rate in a direction along the axis of incidence of the electromagnetic energy, thereby permitting the anisotropic formation of voids within the semiconductor substrate. These anisotropic voids may be more closely spaced (i.e., arranged on a tighter pitch) than the isotropic voids produced using conventional etching technologies. By placing the voids in the semiconductor substrate on a tighter pitch, greater component density may be achieved.

公开(公告)号：US11721631B2

公开(公告)日：2023-08-08

申请号：US17752717

申请日：2022-05-24

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Hiroki Tanaka ,  Oscar Ojeda ,  Arnab Roy ,  Vahidreza Parichehreh ,  Leonel R. Arana ,  Chung Kwang Tan ,  Robert A. May

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5386

Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.